- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384023 > TMS6641648A (Texas Instruments, Inc.) 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES PDF資料下載
參數(shù)資料
| 型號： | TMS6641648A |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 4 194 304 4位/ 2 097 152 8位/ 1 048 576由16位4，銀行同步動態(tài)隨機存取記憶體 |
| 文件頁數(shù)： | 12/56頁 |
| 文件大小： | 958K |
| 代理商： | TMS6641648A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
data/output mask
Masking of individual data cycles within a burst sequence can be accomplished by using the MASK command
(see Table 3). If DQM (or DQML/DQMU of x16) is held high on the rising edge of CLK during a write burst, the
incident data word (referenced to the same rising edge of CLK) on DQ0–DQ7 [or (DQ0–DQ7)/(DQ8–DQ15)
of x16] is ignored. If DQM (or DQML/DQMU of x16) is held high on the rising edge of CLK for a read burst,
DQ0–DQ7 [or (DQ0–DQ7)/(DQ8–DQ15) of x16], referenced to the second rising edge of CLK, are in the
high-impedance state. The application of DQM (DQML/DQMU) to data-output cycles (READ burst) involves a
latency of two CLK cycles, but the application of DQM to data-in cycles (WRITE burst) has no latency. The MASK
command (or its opposite, the ENBL command) is performed on a cycle-by-cycle basis, allowing the user to gate
any individual data cycle or cycles within either a read-burst or a write-burst sequence. Figure 14, Figure 38 and
Figure 39 show examples of data/output masking.
CLK-suspend/power-down mode
For normal device operation, CKE should be held high to enable CLK. If CKE goes low during the execution
of a READ (READ-P) or WRT (WRT-P) operation, the state of the DQ bus occurring at the immediate next rising
edge of CLK is frozen at its current state and no further inputs are accepted until CKE is returned high. This is
known as a CLK-suspend operation and its execution is denoted as a HOLD command. The device resumes
operation from the point at which it was placed in suspension, beginning with the second rising edge of CLK
after CKE is returned high. See Figure 42 and Figure 43 for examples.
If CKE is brought low when no READ (READ-P) or WRT (WRT-P) command is in progress, the device enters
power-down mode. If all banks are deactivated when power-down mode is entered, power consumption is
reduced to the minimum. Power-down mode can be used during row-active or auto-refresh periods to reduce
input-buffer power. After power-down mode has been entered, no further inputs are accepted until CKE returns
high. To ensure that data in the device remains valid during the power-down mode, the self-refresh command
(SLRF) must be executed concurrently with the power-down entry (PDE) command. When exiting power-down
mode, new commands can be entered on the first CLK edge after CKE returns high, provided that the setup
time (t
CESP
) is satisfied. Table 2 shows the command configuration for a CLK-suspend/power-down operation;
Figure 18 and Figure 19 show examples of the procedure.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMS66441410 | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS6644148 | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS6644148A | 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS99534A | FREQUENCY-SHITF-KEYED MODEM |
| TMS99532A | FREQUENCY-SHITF-KEYED MODEM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS664164DGE-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X1MX16|CMOS|TSOP|54PIN|PLASTIC |
| TMS664164DGE-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X1MX16|CMOS|TSOP|54PIN|PLASTIC |
| TMS664164DGE-8A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SDRAM|4X1MX16|CMOS|TSOP|54PIN|PLASTIC |
| TMS664414 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS66441410 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES |
發(fā)布緊急采購，3分鐘左右您將得到回復。