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Device Characteristics
www.ti.com ......................................................................................................................................................... SPNS110E – AUGUST 2005 – REVISED MAY 2008
The A384 device is a derivative of the F05 system emulation device SE470R1VB8AD.
Table 1 identifies all the
characteristics of the A384 device except the SYSTEM and CPU, which are generic.
Table 1. Device Characteristics
TMS470R1A384
CHARACTERISTICS
COMMENTS
DEVICE DESCRIPTION
MEMORY
For the number of memory selects on this device, see
Table 3, TMS470R1A384 Memory Selection Assignment.
Pipeline/non-pipeline
Flash is pipeline capable.
384K-byte flash
The A384 RAM is implemented in one 16K-byte array selected by
Internal Memory
32K-byte SRAM
two memory-select signals (see
Table 3, TMS470R1A384 Memory
Selection Assignment).
PERIPHERALS
For the device-specific interrupt priority configurations, see
Table 6, Interrupt Priority (IEM and CIM). For the 1K-byte peripheral address
ranges and their peripheral selects, see
Table 4, A384 Peripherals, System Module, and Flash Base Addresses.
CLOCK
ZPLL
Zero-pin PLL has no external loop filter pins.
Expansion bus module with 40 pins. Supports 8- and 16-bit
Expansion Bus
EBM
memories, PGE package only. See
Table 7 for details.
In the PGE package, Port A has 8 external pins; Port B has only 1
external pin; Ports C, D, E, F, and G each have 8 external pins; and
55 I/O (PGE suffix)
Port H has 6 external pins.
General-Purpose I/Os
14 I/O (PZ suffix)
In the PZ package, Port A has 8 external pins, Port B has 1 external
pin, and Port H has 5 external pins.
ECP
Yes
SCI
2 (3-pin)
CAN (HECC and/or SCC)
2 SCC
Two standard CAN controllers
SPI (5 pin, 4 pin, or 3 pin)
2 (5-pin)
C2SIb
1
I2C
3
The high-resolution (HR) Share feature allows even-numbered HR
pins to share the next higher odd-numbered HR pin structures. This
HR sharing is independent of whether or not the odd pin is available
HET with XOR Share
12 I/O
externally. If an odd pin is available externally and shared, then the
odd pin can only be used as a general-purpose I/O. For more
information on HR SHARE, see the TMS470R1x High-End Timer
(HET) Reference Guide (literature number SPNU199).
HET RAM
64-instruction capacity
10-bit 12-channel
Both the logic and registers for a full 16-channel MibADC are
MibADC
64-word FIFO
present.
Core Voltage
1.8 V
I/O Voltage
3.3 V
Pins
144/100
PGE/PZ
Copyright 2005–2008, Texas Instruments Incorporated
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