參數資料
型號: TMS32C6416CZLZA6E3
廠商: Texas Instruments, Inc.
元件分類: 數字信號處理
英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述: 定點數字信號處理器
文件頁數: 83/141頁
文件大?。?/td> 2234K
代理商: TMS32C6416CZLZA6E3
TMS320C6414, TMS320C6415, TMS320C6416
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N
FEBRUARY 2001
REVISED MAY 2005
83
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
INPUT AND OUTPUT CLOCKS (CONTINUED)
1
5
6
2
3
ECLKIN
ECLKOUT1
4
4
Figure 20. ECLKOUT1 Timing for EMIFA and EMIFB Modules
switching characteristics over recommended operating conditions for ECLKOUT2 for the EMIFA
and EMIFB modules
§
(see Figure 21)
NO.
PARAMETER
5E0, A
5E0,
6E3, A
6E3,
7E3
UNIT
MIN
MAX
±
175
1
2
3
4
5
6
t
J(EKO2)
t
w(EKO2H)
t
w(EKO2L)
t
t(EKO2)
t
d(EKIH-EKO2H)
t
d(EKIH-EKO2L)
Period jitter, ECLKOUT2
Pulse duration, ECLKOUT2 high
Pulse duration, ECLKOUT2 low
Transition time, ECLKOUT2
Delay time, ECLKIN high to ECLKOUT2 high
Delay time, ECLKIN high to ECLKOUT2 low
0
ps
ns
ns
ns
ns
ns
0.5NE
0.7
0.5NE
0.7
0.5NE + 0.7
0.5NE + 0.7
1
8
8
1
1
The reference points for the rise and fall transitions are measured at V
OL
MAX and V
OH
MIN.
These C64x
devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
§
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
N = the EMIF input clock divider; N = 1, 2, or 4.
This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
5
6
ECLKIN
ECLKOUT2
3
2
4
4
1
Figure 21. ECLKOUT2 Timing for the EMIFA and EMIFB Modules
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