參數(shù)資料
型號(hào)： TMS32C6415EZLZA6E3
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 108/141頁
文件大?。?/td> 2234K
代理商： TMS32C6415EZLZA6E3
TMS320C6414, TMS320C6415, TMS320C6416
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146L
FEBRUARY 2001
REVISED JULY 2004
108
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
HOST-PORT INTERFACE (HPI) TIMING
timing requirements for host-port interface cycles
(see Figure 39 through Figure 46)
NO.
5E0, A
5E0,
6E3, A
6E3,
7E3
UNIT
MIN
5
2.4
4P
4P
5
2
5
2.8
MAX
1
2
3
4
10
11
12
13
t
su(SELV-HSTBL)
t
h(HSTBL-SELV)
t
w(HSTBL)
t
w(HSTBH)
t
su(SELV-HASL)
t
h(HASL-SELV)
t
su(HDV-HSTBH)
t
h(HSTBH-HDV)
Setup time, select signals
§
valid before HSTROBE low
Hold time, select signals
§
valid after HSTROBE low
Pulse duration, HSTROBE low
Pulse duration, HSTROBE high between consecutive accesses
Setup time, select signals
§
valid before HAS low
Hold time, select signals
§
valid after HAS low
Setup time, host data valid before HSTROBE high
Hold time, host data valid after HSTROBE high
Hold time, HSTROBE low after HRDY low. HSTROBE should not be
inactivated until HRDY is active (low); otherwise, HPI writes will not complete
properly.
ns
ns
ns
ns
ns
ns
ns
ns
14
t
h(HRDYL-HSTBL)
2
ns
18
19
t
su(HASL-HSTBL)
t
h(HSTBL-HASL)
Setup time, HAS low before HSTROBE low
Hold time, HAS low after HSTROBE low
2
ns
ns
2.1
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
§
Select signals include: HCNTL[1:0] and HR/W. For HPI16 mode only, select signals also include HHWIL.
Select the parameter value of 4P or 12.5 ns, whichever is greater.
switching characteristics over recommended operating conditions during host-port interface
cycles
(see Figure 39 through Figure 46)
NO.
PARAMETER
5E0
6E3
7E3
A
5E0
A
6E3
UNIT
MIN
1.3
MAX
4P + 8
MIN
1.3
MAX
4P + 9
6
t
d(HSTBL-HRDYH)
Delay time, HSTROBE low to HRDY high
#
ns
7
t
d(HSTBL-HDLZ)
Delay time, HSTROBE low to HD low impedance for an
HPI read
2
2
ns
8
9
15
t
d(HDV-HRDYL)
t
oh(HSTBH-HDV)
t
d(HSTBH-HDHZ)
Delay time, HD valid to HRDY low
Output hold time, HD valid after HSTROBE high
Delay time, HSTROBE high to HD high impedance
3
1.5
3
1.5
ns
ns
ns
12
12
16
t
d(HSTBL-HDV)
Delay time, HSTROBE low to HD valid
(HPI16 mode, 2nd half-word only)
4P + 8
4P + 8
ns
HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
#
This parameter is used during HPID reads and writes. For reads, at the beginning of a word transfer (HPI32) or the first half-word transfer (HPI16)
on the falling edge of HSTROBE, the HPI sends the request to the EDMA internal address generation hardware, and HRDY remains high until
the EDMA internal address generation hardware loads the requested data into HPID. For writes, HRDY goes high if the internal write buffer is
full.
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