參數(shù)資料
型號(hào)： TMS32C6415EGLSA6E3
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 82/141頁
文件大?。?/td> 2234K
代理商： TMS32C6415EGLSA6E3
TMS320C6414, TMS320C6415, TMS320C6416
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N
FEBRUARY 2001
REVISED MAY 2005
82
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
INPUT AND OUTPUT CLOCKS (CONTINUED)
timing requirements for ECLKIN for EMIFA and EMIFB
§
(see Figure 19)
NO.
5E0, A
5E0,
6E3, A
6E3,
7E3
UNIT
MIN
6
#
2.7
2.7
MAX
16P
1
2
3
4
t
c(EKI)
t
w(EKIH)
t
w(EKIL)
t
t(EKI)
t
J(EKI)
Cycle time, ECLKIN
Pulse duration, ECLKIN high
Pulse duration, ECLKIN low
Transition time, ECLKIN
ns
ns
ns
ns
2
5
Period jitter, ECLKIN
0.02E
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.
The reference points for the rise and fall transitions are measured at V
IL
MAX and V
IH
MIN.
§
These C64x
devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
#
Minimum ECLKIN cycle times
must
be met, even when ECLKIN is generated by an internal clock source. Minimum ECLKIN times are based
on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements. On the 7E3 and 6E3 devices,
133-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. On the 5E0 devices, 100-MHz operation is
achievable if the requirements of the EMIF Device Speed section are met.
ECLKIN
2
3
4
4
5
1
Figure 19. ECLKIN Timing for EMIFA and EMIFB
switching characteristics over recommended operating conditions for ECLKOUT1 for EMIFA and
EMIFB modules
§||
(see Figure 20)
NO.
PARAMETER
5E0, A
5E0,
6E3, A
6E3,
7E3
UNIT
MIN
MAX
±
175
EH + 0.7
EL + 0.7
1
2
3
4
5
6
t
J(EKO1)
t
w(EKO1H)
t
w(EKO1L)
t
t(EKO1)
t
d(EKIH-EKO1H)
t
d(EKIL-EKO1L)
Period jitter, ECLKOUT1
Pulse duration, ECLKOUT1 high
Pulse duration, ECLKOUT1 low
Transition time, ECLKOUT1
Delay time, ECLKIN high to ECLKOUT1 high
Delay time, ECLKIN low to ECLKOUT1 low
0
ps
ns
ns
ns
ns
ns
EH
0.7
EL
0.7
1
8
8
1
1
§
These C64x
devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are
prefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
||
The reference points for the rise and fall transitions are measured at V
OL
MAX and V
OH
MIN.
EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns for EMIFA or EMIFB.
This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
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