參數(shù)資料
型號： TMS32C6415CZLZA6E3
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 85/141頁
文件大?。?/td> 2234K
代理商： TMS32C6415CZLZA6E3
TMS320C6414, TMS320C6415, TMS320C6416
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N
FEBRUARY 2001
REVISED MAY 2005
85
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
ASYNCHRONOUS MEMORY TIMING (CONTINUED)
timing requirements for asynchronous memory cycles for EMIFB module
§
(see Figure 22 and Figure 23)
NO.
5E0
6E3
7E3
A
5E0
A
6E3
UNIT
MIN
6.2
MAX
MIN
6.2
MAX
3
4
6
t
su(EDV-AREH)
t
h(AREH-EDV)
t
su(ARDY-EKO1H)
Setup time, EDx valid before ARE high
Hold time, EDx valid after ARE high
Setup time, ARDY valid before ECLKOUTx high
ns
ns
ns
1
3
1
3
7
t
h(EKO1H-ARDY)
Hold time, ARDY valid after ECLKOUTx high
Rev 1.1 and
earlier
1.2
1.7
ns
Rev 2.0
1.3
1.7
ns
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is
only
recognized
two cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY is
recognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse width
of the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§
These C64x
devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous
memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and
BAWE (for EMIFB)].
switching characteristics over recommended operating conditions for asynchronous memory
cycles for EMIFB module
§#
(see Figure 22 and Figure 23)
NO.
PARAMETER
5E0, A
5E0,
6E3, A
6E3,
7E3
UNIT
MIN
MAX
1
2
5
8
9
10
t
osu(SELV-AREL)
t
oh(AREH-SELIV)
t
d(EKO1H-AREV)
t
osu(SELV-AWEL)
t
oh(AWEH-SELIV)
t
d(EKO1H-AWEV)
Output setup time, select signals valid to ARE low
Output hold time, ARE high to select signals invalid
Delay time, ECLKOUTx high to ARE valid
Output setup time, select signals valid to AWE low
Output hold time, AWE high to select signals invalid
Delay time, ECLKOUTx high to AWE valid
RS * E
1.6
RH * E
1.7
ns
ns
ns
ns
ns
ns
0.8
6.6
WS * E
1.9
WH * E
1.7
0.9
6.7
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§
These C64x
devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a
“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronous
memory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, and
BAWE (for EMIFB)].
E = ECLKOUT1 period in ns for EMIFA or EMIFB
#
Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0].
Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0].
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