參數(shù)資料
型號： TMS32C6415CZLZA6E3
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 43/141頁
文件大?。?/td> 2234K
代理商： TMS32C6415CZLZA6E3
TMS320C6414, TMS320C6415, TMS320C6416
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N
FEBRUARY 2001
REVISED MAY 2005
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Terminal Functions (Continued)
SIGNAL
NAME
TYPE
IPD/
IPU
DESCRIPTION
NO.
RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS
I
Device reset
I
IPD
Nonmaskable interrupt, edge-driven (rising edge)
RESET
NMI
GP7/EXT_INT7
GP6/EXT_INT6
GP5/EXT_INT5
GP4/EXT_INT4
GP15/PRST
§
GP14/PCLK
§
GP13/PINTA
§
GP12/PGNT
§
GP11/PREQ
§
GP10/PCBE3
§
GP9/PIDSEL
§
GP3
AC7
B4
AF4
AD5
AE5
AF5
G3
F2
G4
J3
F1
L2
M3
AC6
General-purpose input/output (GPIO) pins (
General purpose input/output (GPIO) pins (
I/O/Z
) or external interrupts (
input only
). The
default after reset setting is GPIO enabled as input-only.
When these pins function as External Interrupts [by selecting the corresponding interrupt
enable register bit (IER.[7:4])], they are edge-driven and the polarity can be
independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]).
General-purpose input/output (GPIO) 15 pin (
I/O/Z
) or PCI reset (
I
). No function at default.
GPIO 14 pin (
I/O/Z
) or PCI clock (
I
). No function at default.
GPIO 13 pin (
I/O/Z
) or PCI interrupt A (
O/Z
). No function at default.
GPIO 12 pin (
I/O/Z
) or PCI bus grant (
I
). No function at default.
GPIO 11 pin (
I/O/Z
) or PCI bus request (
O/Z
). No function at default.
GPIO 10 pin (
I/O/Z
) or PCI command/byte enable 3 (
I/O/Z
). No function at default.
GPIO 9 pin (
I/O/Z
) or PCI initialization device select (
I
). No function at default.
GPIO 3 pin (
I/O/Z
). The default after reset setting is GPIO 3 enabled as input-only.
GPIO 0 pin.
The general-purpose I/O 0 pin (GPIO 0) (
I/O/Z
) can be programmed as GPIO 0 (
input only
)
[default] or as GPIO 0 (
output only
) pin or output as a general-purpose interrupt (GP0INT)
signal (
output only
).
McBSP2 external clock source (CLKS2) [
input only
] [default] or this pin can be pro-
grammed as a GPIO 8 pin (
I/O/Z
).
I/O/Z
IPU
I/O/Z
IPD
GP0
AF6
IPD
CLKS2/GP8
§
AE4
I/O/Z
IPD
CLKOUT6/GP2
§
AD6
I/O/Z
IPD
Clock output at 1/6 of the device speed (
O/Z
) [default] or this pin can be programmed as a
GPIO 2 pin (
I/O/Z
).
CLKOUT4/GP1
§
AE6
I/O/Z
IPD
Clock output at 1/4 of the device speed (
O/Z
) [default] or this pin can be programmed as a
GPIO 1 pin (
I/O/Z
).
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only]
PCI enable pin. This pin controls the selection (enable/disable) of the HPI and GP[15:9], or
PCI peripherals (for the C6415 and C6416 devices). This pin works in conjunction with the
MCBSP2_EN pin to enable/disable other peripherals (for more details, see the Device Con-
figurations section of this data sheet).
PCI_EN
AA4
I
IPD
The C6414 device does
not
support the PCI peripheral; for proper device operation, do
not
oppose the internal pulldown (IPD) on this pin.
HINT/PFRAME
§
HCNTL1/
PDEVSEL
§
R4
I/O/Z
Host interrupt from DSP to host (
O
) [default] or PCI frame (
I/O/Z
)
Host control
selects between control, address, or data registers (
I
) [default] or PCI device
select (
I/O/Z
).
R1
I/O/Z
HCNTL0/
PSTOP
§
T4
I/O/Z
Host control
selects between control, address, or data registers (
I
) [default] or PCI stop
(
I/O/Z
)
HHWIL/PTRDY
§
R3
I/O/Z
Host half-word select
first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (
I
) [default] or PCI target ready (
I/O/Z
)
HR/W/PCBE2
§
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§
For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414 device does
not
support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions
for this device.
For the C6414 device, only these pins are multiplexed pins.
P1
I/O/Z
Host read or write select (
I
) [default] or PCI command/byte enable 2 (
I/O/Z
)
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