參數(shù)資料
型號: TMS32C6415CGLSA6E3
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 44/141頁
文件大?。?/td> 2234K
代理商: TMS32C6415CGLSA6E3
TMS320C6414, TMS320C6415, TMS320C6416
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N
FEBRUARY 2001
REVISED MAY 2005
44
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Terminal Functions (Continued)
SIGNAL
NAME
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only]
(CONTINUED)
HAS/PPAR
§
T3
I/O/Z
Host address strobe (
I
) [default] or PCI parity (
I/O/Z
)
HCS/PPERR
§
R2
I/O/Z
Host chip select (
I
) [default] or PCI parity error (
I/O/Z
)
HDS1/PSERR
§
T1
I/O/Z
Host data strobe 1 (
I
) [default] or PCI system error (
I/O/Z
)
HDS2/PCBE1
§
T2
I/O/Z
Host data strobe 2 (
I
) [default] or PCI command/byte enable 1 (
I/O/Z
)
HRDY/PIRDY
§
P4
I/O/Z
Host ready from DSP to host (
O
) [default] or PCI initiator ready (
I/O/Z
).
HD31/AD31
§
J2
HD30/AD30
§
K3
HD29/AD29
§
J1
HD28/AD28
§
K4
HD27/AD27
§
K2
HD26/AD26
§
L3
HD25/AD25
§
K1
HD24/AD24
§
L4
HD23/AD23
§
L1
HD22/AD22
§
M4
Host-port data (
I/O/Z
) [default] (C64x) or PCI data-address bus (
I/O/Z
) [C6415 and C6416]
HD21/AD21
§
M2
As HPI data bus (PCI EN pin = 0)
HD20/AD20
§
N4
HD19/AD19
§
M1
HD18/AD18
§
N5
HD17/AD17
§
N1
HD5 pin = 0: HPI operates as an HPI16.
HD16/AD16
§
P5
reserved pins in the high impedance state )
HD15/AD15
§
U4
HD14/AD14
§
U1
HD5 p
HD13/AD13
§
U3
HD12/AD12
§
U2
As PCI data-address bus (PCI EN pin = 1) [C6415 and C6416 devices only]
HD11/AD11
§
V4
Used for transfer of data and address
HD10/AD10
§
V1
support the PCI peripheral; therefore the HPI peripheral pins are
HD9/AD9
§
V3
HD8/AD8
§
V2
HD7/AD7
§
W2
HD6/AD6
§
W4
HD5/AD5
§
Y1
HD4/AD4
§
Y3
HD3/AD3
§
Y2
HD2/AD2
§
Y4
HD1/AD1
§
AA1
HD0/AD0
§
AA3
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§
For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414 device does
not
support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions
for this device.
TYPE
IPD/
IPU
DESCRIPTION
NO.
As HPI data bus (PCI_EN pin = 0)
Used for transfer of data, address, and control
Host-Port bus width user-configurable at device reset via a 10-k
resistor pullup/pulldown
resistor on the HD5 pin:
HD5 pin 0: HPI operates as an HPI16.
(HPI bus is 16 bits wide. HD[15:0] pins are used and the remaining HD[31:16] pins are
reserved pins in the high-impedance state.)
I/O/Z
ope a es as a
3
(HPI bus is 32 bits wide. All HD[31:0] pins are used for host-port operations.)
As PCI data-address bus (PCI_EN pin = 1) [C6415 and C6416 devices only]
The C6414 device does
not
support the PCI peripheral; therefore, the HPI peripheral pins are
standalone peripheral functions, not muxed.
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