參數(shù)資料
型號： TMS32C6414DGLSA6E3
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點數(shù)字信號處理器
文件頁數(shù)： 42/141頁
文件大?。?/td> 2234K
代理商： TMS32C6414DGLSA6E3
TMS320C6414, TMS320C6415, TMS320C6416
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N
FEBRUARY 2001
REVISED MAY 2005
42
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Terminal Functions
SIGNAL
NAME
TYPE
IPD/
IPU
DESCRIPTION
NO.
CLOCK/PLL CONFIGURATION
Clock Input. This clock is the input to the on-chip PLL.
Clock output at 1/4 of the device speed (
O/Z
) [default] or this pin can be programmed as a
GPIO 1 pin (
I/O/Z
).
CLKIN
H4
I
IPD
CLKOUT4/GP1
§
AE6
I/O/Z
IPD
CLKOUT6/GP2
§
AD6
I/O/Z
IPD
Clock output at 1/6 of the device speed (
O/Z
) [default] or this pin can be programmed as a
GPIO 2 pin (
I/O/Z
).
CLKMODE1
G1
I
IPD
Clock mode select
Selects whether the CPU clock frequency = input clock frequency x1 (Bypass), x6, or x12.
For more details on the CLKMODE pins and the PLL multiply factors, see the Clock
PLL
section of this data sheet.
PLL voltage supply
JTAG EMULATION
JTAG test-port mode select
JTAG test-port data out
JTAG test-port data in
JTAG test-port clock
JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1 JTAG
Compatibility Statement section of this data sheet.
CLKMODE0
H2
I
IPD
PLLV
J6
A
#
TMS
TDO
TDI
TCK
AB16
AE19
AF18
AF16
I
IPU
IPU
IPU
IPU
O/Z
I
I
TRST
AB15
I
IPD
EMU11
EMU10
EMU9
EMU8
EMU7
EMU6
EMU5
EMU4
EMU3
EMU2
AC18
AD18
AE18
AC17
AF17
AD17
AE17
AC16
AD16
AE16
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
Emulation pin 11. Reserved for future use, leave unconnected.
Emulation pin 10. Reserved for future use, leave unconnected.
Emulation pin 9. Reserved for future use, leave unconnected.
Emulation pin 8. Reserved for future use, leave unconnected.
Emulation pin 7. Reserved for future use, leave unconnected.
Emulation pin 6. Reserved for future use, leave unconnected.
Emulation pin 5. Reserved for future use, leave unconnected.
Emulation pin 4. Reserved for future use, leave unconnected.
Emulation pin 3. Reserved for future use, leave unconnected.
Emulation pin 2. Reserved for future use, leave unconnected.
Emulation [1:0] pins
Select the device functional mode of operation
EMU[1:0]
Operation
00
Boundary Scan/Normal Mode (see Note)
01
Reserved
10
Reserved
11
Emulation/Normal Mode [default] (see the IEEE 1149.1 JTAG
Compatibility Statement section of this data sheet)
Normal mode refers to the DSPs normal operational mode, when the DSP is free running. The
DSP can be placed in normal operational mode when the EMU[1:0] pins are configured for
either Boundary Scan or Emulation.
EMU1
EMU0
AC15
AF15
I/O/Z
IPU
Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the internal pulldown
(IPD) on the TRST signal must
not
be opposed in order to operate in Normal mode.
For the Boundary Scan mode pulldown EMU[1:0] pins with a dedicated 1-k
resister.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
#
A = Analog signal (PLL Filter)
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