參數(shù)資料
型號： TMS32C6414CZLZA6E3
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSORS
中文描述： 定點(diǎn)數(shù)字信號處理器
文件頁數(shù)： 51/141頁
文件大?。?/td> 2234K
代理商： TMS32C6414CZLZA6E3
TMS320C6414, TMS320C6415, TMS320C6416
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N
FEBRUARY 2001
REVISED MAY 2005
51
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Terminal Functions (Continued)
SIGNAL
NAME
TYPE
IPD/
IPU
DESCRIPTION
NO.
EMIFB (16-bit)
DATA
||
BED15
BED14
BED13
BED12
BED11
BED10
BED9
BED8
BED7
BED6
BED5
BED4
BED3
BED2
BED1
BED0
D7
B6
C7
A6
D8
B7
C8
A7
C9
B8
D9
B9
C10
A9
D10
B10
I/O/Z
IPU
EMIFB external data
MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP2)
McBSP2 enable pin. This pin works in conjunction with the PCI_EN pin to enable/disable other
peripherals (for more details, see the Device Configurations section of this data sheet).
MCBSP2_EN
AF3
I
IPD
CLKS2/GP8
§
AE4
I/O/Z
IPD
McBSP2 external clock source (CLKS2) [
input only
] [default] or this pin can also be
programmed as a GPIO 8 pin (
I/O/Z
).
CLKR2
AB1
I/O/Z
IPD
McBSP2 receive clock. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin = 0),
this pin is tied-off.
CLKX2/
XSP_CLK
§
AC2
I/O/Z
IPD
McBSP2 transmit clock (
I/O/Z
) [default] or PCI serial interface clock (
O
).
DR2/XSP_DI
§
AB3
I
IPU
McBSP2 receive data (
I
) [default] or PCI serial interface data in (
I
). In PCI mode, this pin is
connected to the output data pin of the serial PROM.
DX2/XSP_DO
§
AA2
O/Z
IPU
McBSP2 transmit data (
O/Z
) [default] or PCI serial interface data out (
O
). In PCI mode, this pin
is connected to the input data pin of the serial PROM.
FSR2
AC1
I/O/Z
IPD
McBSP2 receive frame sync. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin
= 0), this pin is tied-off.
FSX2
AB2
I/O/Z
IPD
McBSP2 transmit frame sync. When McBSP2 is disabled (PCI_EN = 1 and MCBSP2_EN pin
= 0), this pin is tied-off.
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§
For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414 device does
not
support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins except CLKS2/GP8 are standalone
peripheral functions for this device.
||
These C64x
devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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