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| 型號(hào)： | TMS32C6414CZLZA6E3 |
| 廠(chǎng)商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 45/141頁(yè) |
| 文件大小： | 2234K |
| 代理商： | TMS32C6414CZLZA6E3 |
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TMS320C6414, TMS320C6415, TMS320C6416
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N
FEBRUARY 2001
REVISED MAY 2005
45
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Terminal Functions (Continued)
SIGNAL
NAME
HOST-PORT INTERFACE (HPI) [C64x] or PERIPHERAL COMPONENT INTERCONNECT (PCI) [C6415 or C6416 devices only]
(CONTINUED)
TYPE
IPD/
IPU
DESCRIPTION
NO.
PCBE0
W3
I/O/Z
PCI command/byte enable 0 (
I/O/Z
). When PCI is disabled (PCI_EN = 0), this pin is tied-off.
For the C6414 device this pin is “Reserved (leave unconnected,
do not
connect to power or
ground).”
XSP_CS
AD1
O
IPD
PCI serial interface chip select (
O
). When PCI is disabled (PCI_EN = 0), this pin is tied-off.
For the C6414 device this pin is “Reserved (leave unconnected,
do not
connect to power or
ground).”
CLKX2/
XSP_CLK
§
AC2
I/O/Z
IPD
McBSP2 transmit clock (
I/O/Z
) [default] or PCI serial interface clock (
O
) (PCI_EN = 1).
DR2/XSP_DI
§
AB3
I
IPU
McBSP2 receive data (
I
) [default] or PCI serial interface data in (
I
). In PCI mode (PCI_EN = 1),
this pin is connected to the output data pin of the serial PROM.
DX2/XSP_DO
§
AA2
O/Z
IPU
McBSP2 transmit data (
O/Z
) [default] or PCI serial interface data out (
O
). In PCI mode
(PCI_EN = 1), this pin is connected to the input data pin of the serial PROM.
GP15/PRST
§
GP14/PCLK
§
GP13/PINTA
§
GP12/PGNT
§
GP11/PREQ
§
GP10/PCBE3
§
GP9/PIDSEL
§
G3
F2
G4
J3
F1
L2
M3
General-purpose input/output (GPIO) 15 pin (
I/O/Z
) or PCI reset (
I
). No function at default.
GPIO 14 pin (
I/O/Z
) or PCI clock (
I
). No function at default.
GPIO 13 pin (
I/O/Z
) or PCI interrupt A (
O/Z
). No function at default.
GPIO 12 pin (
I/O/Z
) or PCI bus grant (
I
). No function at default.
GPIO 11 pin (
I/O/Z
) or PCI bus request (
O/Z
). No function at default.
GPIO 10 pin (
I/O/Z
) or PCI command/byte enable 3 (
I/O/Z
). No function at default.
GPIO 9 pin (
I/O/Z
) or PCI initialization device select (
I
). No function at default.
EMIFA (64-bit)
CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY
||
O/Z
IPU
O/Z
IPU
O/Z
IPU
O/Z
IPU
O/Z
IPU
O/Z
IPU
O/Z
IPU
EMIFA byte-enable control
O/Z
IPU
O/Z
IPU
O/Z
IPU
O/Z
IPU
O/Z
IPU
O/Z
IPU
EMIFA peripheral data transfer, allows direct transfer between external peripherals
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§
For the C6415 and C6416 devices, these pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
The C6414 device does
not
support the PCI or UTOPIA peripherals; therefore, these muxed peripheral pins are standalone peripheral functions
for this device.
||
These C64x
devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix “A” in front of a signal name indicates it is an EMIFA signal
whereas a prefix “B” in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of
discussion, the prefix “A” or “B” may be omitted from the signal name.
To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
I/O/Z
ACE3
ACE2
ACE1
ACE0
ABE7
ABE6
ABE5
ABE4
ABE3
ABE2
ABE1
ABE0
APDT
L26
K23
K24
K25
T23
T24
R25
R26
M25
M26
L23
L24
M22
EMIFA memory space enables
Enabled by bits 28 through 31 of the word address
Only one pin is asserted during any external data access
EMIFA byte enable control
Decoded from the low-order address bits. The number of address bits or byte enables
used depends on the width of external memory.
Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
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