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參數(shù)資料
| 型號： | TMS320LFC2406A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP CONTROLLERS |
| 中文描述： | DSP控制器 |
| 文件頁數(shù)： | 52/133頁 |
| 文件大?。?/td> | 1672K |
| 代理商： | TMS320LFC2406A |
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SPRS145J JULY 2000 REVISED NOVEMBER 2004
52
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controller area network (CAN) module (continued)
The mailboxes are situated in one 48-word x 16-bit RAM. It can be written to or read by the CPU or the CAN.
The CAN write or read access, as well as the CPU read access, needs one clock cycle. The CPU write access
needs two clock cycles. In these two clock cycles, the CAN performs a read-modify-write cycle and, therefore,
inserts one wait state for the CPU.
Address bit 0 of the address bus used when accessing the RAM decides if the lower (0) or the higher (1)
16-bit word of the 32-bit word is taken. The RAM location is determined by the upper bits 5 to 1 of the address
bus.
Table 8. 3.3-V CAN Transceivers for the TMS320Lx240xA DSPs
PART NUMBER
LOW-POWER MODE
INTEGRATED
SLOPE CONTROL
Vref PIN
TA
MARKED AS
SN65HVD230
370
μ
A standby mode
40 nA sleep mode
No standby or sleep mode
Yes
Yes
VP230
SN65HVD231
SN65HVD232
This is the nomenclature printed on the device, since the footprint is too small to accommodate the entire part number.
Yes
No
Yes
No
40 C to 85 C
VP231
VP232
CAN interrupt logic
There are two interrupt requests from the CAN module to the peripheral interrupt expansion (PIE) controller:
the mailbox interrupt and the error interrupt. Both interrupts can assert either a high-priority request or a
low-priority request to the CPU. Since CAN mailboxes can generate multiple interrupts, the software should
read the CAN_IFR register for every interrupt and prioritize the interrupt service, or else, these multiple
interrupts will not be recognized by the CPU and PIE hardware logic. Each interrupt routine should service all
the interrupt bits that are set and clear them after service.
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