參數(shù)資料
型號： TMS320LF2406PGS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DSP CONTROLLERS
中文描述： DSP控制器
文件頁數(shù)： 2/115頁
文件大小： 1511K
代理商： TMS320LF2406PGS
SPRS094I APRIL 1999 REVISED SEPTEMBER 2003
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Description
TMS320x240x Device Summary
Functional Block Diagram of the 2407 DSP Controller
Pin Functions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Maps
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Memory Map of the LF240x
Device Reset and Interrupts
DSP CPU Core
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMS320x240x Instruction Set
Functional Block Diagram
of the 240x DSP CPU
Peripherals
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Event Manager Modules (EVA, EVB)
Enhanced Analog-to-Digital Converter
(ADC) Module
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5
6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . .
10
17
20
21
25
25
26
35
35
. . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . .
. . . .
. . . . . . . . . . . .
39
Controller Area Network (CAN) Module
Serial Communications Interface (SCI) Module
Serial Peripheral Interface (SPI) Module
PLL-Based Clock Module
Digital I/O and Shared Pin Functions
External Memory Interface (LF2407)
Watchdog (WD) Timer Module
Development Support
. . . . . . . . . . . . . . . . . . . . . . . . . . .
Documentation Support
. . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings
Recommended Operating Conditions
Peripheral Register Description
Mechanical Data
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
44
46
48
51
54
55
58
61
62
62
99
112
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. . . .
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. . . . . . . . . . . . . . . . . . . . . .
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Table of Contents
REVISION HISTORY
REVISION
DATE
PRODUCT STATUS
HIGHLIGHTS
F
January 2001
Production Data
The description for the VCCP pin has been modified. This informa-
tion can be found in Table 2, LF240x Pin List and Package Options.
The conditions for high-impedance state for the strobe signals have
been changed. This information can be found in Table 2, LF240x Pin
List and Package Options.
The th(A)COLW parameter is now referenced from the next falling
CLKOUT edge than what was shown in the previous data sheets.
The specification for this parameter is 5 ns (MIN).
Ready-on-Read and Ready-on-Write timings for one software wait
state and one external wait state have been added.
Bits 15 and 8 of the SCSR1 register are now reserved
(see Table 19, LF240x DSP Peripheral Register Description).
G
August 2001
Production Data
Updated description of TMS2 in Table 2.
Updated Figure 6, Event Manager A Block Diagram. TCLKINx is
now routed through the prescaler.
Updated the ADC module list of functions in the Enhanced Analog-
to-Digital Converter (ADC) Module section (p.39).
The I/O buffers used in 240x/240xA are
not
5-V compatible.
Updated the fCLKOUT parameter in the Recommended Operating
Conditions table (p.62).
Updated the tc(AD) and tw(SHC) parameters in the Internal ADC Mod-
ule Timings table of the 10-Bit Analog-to-Digital Converter (ADC)
section (p.97).
Updated PDDATDIR register (0x0709E) in Table 19, LF240x DSP
Peripheral Register Description.
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