參數(shù)資料
型號(hào): TMS320LC57PBKA80
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 72/87頁(yè)
文件大?。?/td> 1259K
代理商: TMS320LC57PBKA80
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
72
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
SERIAL-PORT RECEIVE TIMING IN TDM MODE
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = 0.5t
c(CO)
] (see Figure 25)
’320C5x-40
’320C5x-57
’320LC5x-40
’320LC5x-50
MIN
5.2H
’320C5x-80
’320LC5x-80
’320C5x-100
UNIT
MAX
MIN
5.2H
MAX
MIN
5.2H§
MAX
tc(SCK)
tf(SCK)
tr(SCK)
tw(SCK)
tsu(TD-TCH)
th(TCH-TD)
tsu(TA-TCH)
th(TCH-TA)
tsu(TF-TCH)
th(TCH-TF)
Values ensured by design and are not tested
The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching
. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
§TFRM timing and waveforms shown in Figure 25 are for external TFRM. TFRM also can be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 26.
Values derived from characterization data and not tested
#These parameters apply only to the first bits in the serial bit string.
Cycle time, serial-port clock
ns
Fall time, serial-port clock
8
8
8
8
8
8
ns
Rise time, serial-port clock
ns
Pulse duration, serial-port clock low/high
2.1H
2.1H
2.1H
ns
Setup time, TDAT before TCLK rising edge
30
21
18
ns
Hold time, TDAT after TCLK rising edge
Setup time, TADD before TCLK rising edge#
Hold time, TADD after TCLK rising edge#
Setup time, TFRM before TCLK rising edge§
Hold time, TFRM after TCLK rising edge§
– 3
– 2
– 2
ns
20
12
10
ns
– 3
– 2
– 2
ns
10
10
10
ns
10
10
10
ns
A7
B2
B8
B7
A3
B12
A2
A0
A1
B0
B1
B13
B14
B15
B0
tw(SCK)
tw(SCK)
tsu(TD-TCH)
th(TCH-TD)
tsu(TA-TCH)
th(TCH-TA)
tr(SCK)
tf(SCK)
tc(SCK)
TFRM
TADD
TDAT
TCLK
th(TCH-TF)
tsu(TF-TCH)
th(TCH-TA)
Figure 25. Serial-Port Receive Timing in TDM Mode
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