參數(shù)資料
型號: TMS320LC57PBKA80
元件分類: 數(shù)字信號處理
英文描述: 16-Bit Digital Signal Processor
中文描述: 16位數(shù)字信號處理器
文件頁數(shù): 49/87頁
文件大?。?/td> 1259K
代理商: TMS320LC57PBKA80
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
49
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLoad
IOL
C
T
IOH
Output
Under
Test
50
Where:
IOL
IOH
VLOAD
CT
Figure 9. Test Load Circuit
=
=
=
=
2 mA (all outputs) minimum
300
μ
A (all outputs) minimum
1.5 V
80-pF typical load circuit capacitance
signal transition levels
The data in this section is shown for both the 5-V version (’C5x) and the 3.3-V version (’LC5x). In each case,
the 5-V data is shown followed by the 3.3-V data in parentheses. TTL-output levels are driven to a minimum
logic-high level of 2.4 V (2 V) and to a maximum logic-low level of 0.6 V (0.4 V). Figure 10 shows the TTL-level
outputs.
0.6 V (0.4 V)
1 V (0.8 V)
2 V (1.6 V)
2.4 V (2 V)
Figure 10. TTL-Level Outputs
TTL-output transition times are specified as follows:
For a high-to-low transition the level at which the output is said to be no longer high is 2 V (1.6 V), and the
level at which the output is said to be low is 1 V (0.8 V).
For a low-to-high transition the level at which the output is said to be no longer low is 1 V (0.8 V), and the
level at which the output is said to be high is 2 V (1.6 V).
Figure 11 shows the TTL-level inputs.
2 V (1.8 V)
0.8 V (0.6 V)
Figure 11. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
For a high-to-low transitionon an input signal, the level at which the input is said to be no longer high is
2 V (1.8 V), and the level at which the input is said to be low is 0.8 V (0.6 V).
For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.8 V (0.6 V), and the level at which the input is said to be high is 2 V (1.8 V).
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