參數(shù)資料
型號： TMS320F2810GHHMEP
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Digital Signal Processors
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 76/159頁
文件大?。?/td> 2084K
代理商： TMS320F2810GHHMEP
Peripherals
76
March 2004 Revised October 2004
SGUS051A
NRZ (non-return-to-zero) format
Ten SCI module control registers located in the control register frame beginning at address 7050h
NOTE:
register is accessed, the register data is in the lower byte (70), and the upper byte (158) is read as
zeros. Writing to the upper byte has no effect.
All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a
Enhanced features:
Auto baud-detect hardware logic
16-level transmit/receive FIFO
The SCI port operation is configured and controlled by the registers listed in Table 48 and Table 49.
Table 48. SCI-A Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
SCICCRA
0x00 7050
1
SCI-A Communications Control Register
SCICTL1A
0x00 7051
1
SCI-A Control Register 1
SCIHBAUDA
0x00 7052
1
SCI-A Baud Register, High Bits
SCILBAUDA
0x00 7053
1
SCI-A Baud Register, Low Bits
SCICTL2A
0x00 7054
1
SCI-A Control Register 2
SCIRXSTA
0x00 7055
1
SCI-A Receive Status Register
SCIRXEMUA
0x00 7056
1
SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA
0x00 7057
1
SCI-A Receive Data Buffer Register
SCITXBUFA
0x00 7059
1
SCI-A Transmit Data Buffer Register
SCIFFTXA
0x00 705A
1
SCI-A FIFO Transmit Register
SCIFFRXA
0x00 705B
1
SCI-A FIFO Receive Register
SCIFFCTA
0x00 705C
1
SCI-A FIFO Control Register
SCIPRIA
0x00 705F
1
SCI-A Priority Control Register
Shaded registers are new registers for the FIFO mode.
Table 49. SCI-B Registers
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
SCICCRB
0x00 7750
1
SCI-B Communications Control Register
SCICTL1B
0x00 7751
1
SCI-B Control Register 1
SCIHBAUDB
0x00 7752
1
SCI-B Baud Register, High Bits
SCILBAUDB
0x00 7753
1
SCI-B Baud Register, Low Bits
SCICTL2B
0x00 7754
1
SCI-B Control Register 2
SCIRXSTB
0x00 7755
1
SCI-B Receive Status Register
SCIRXEMUB
0x00 7756
1
SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB
0x00 7757
1
SCI-B Receive Data Buffer Register
SCITXBUFB
0x00 7759
1
SCI-B Transmit Data Buffer Register
SCIFFTXB
0x00 775A
1
SCI-B FIFO Transmit Register
SCIFFRXB
0x00 775B
1
SCI-B FIFO Receive Register
SCIFFCTB
0x00 775C
1
SCI-B FIFO Control Register
SCIPRIB
0x00 775F
1
SCI-B Priority Control Register
Shaded registers are new registers for the FIFO mode.
Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results.
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