參數(shù)資料
型號(hào): TMS320DM648ZUT9
廠商: Texas Instruments
文件頁(yè)數(shù): 103/190頁(yè)
文件大?。?/td> 0K
描述: IC DGTL MEDIA PROC 529-FCBGA
標(biāo)準(zhǔn)包裝: 84
系列: TMS320DM64x, DaVinci™
類型: 定點(diǎn)
接口: 主機(jī)接口,I²C,McASP,PCI,SPI,UART
時(shí)鐘速率: 900MHz
非易失內(nèi)存: ROM(64 kB)
芯片上RAM: 576kB
電壓 - 輸入/輸出: 1.8V,3.3V
電壓 - 核心: 1.20V
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 529-BFBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 529-FCBGA(19x19)
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 715 (CN2011-ZH PDF)
配用: 296-23122-ND - PLATFORM DEV DGTL VIDEO DM648
其它名稱: 296-26858-5
TMS320DM648ZUT9-ND
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SPRS372H – MAY 2007 – REVISED APRIL 2012
VLYNQ Interface (FPGA Interface)
(Multiplexed With Other Device Functions)
On-Chip ROM Bootloader
Package:
Individual Power-Saving Modes
– 529-pin nFBGA (ZUT suffix)
Flexible PLL Clock Generators
– 19x19 mm 0.8 mm pitch BGA
IEEE-1149.1 (JTAG) Boundary-Scan-
– 0.09-
μm/6-Level Cu Metal Process (CMOS)
Compatible
3.3-V and 1.8-V I/O, 1.2-V Internal (-720, -800, -
32 General-Purpose I/O (GPIO) Pins
900, -1100)
1.1
Applications
Digital Video Recording
1.2
Trademarks
TMS320C64x+, C64x, C64x+, VelociTI, VelociTI.2, VLYNQ, TMS320C6000, C6000, TI, and TMS320 are
trademarks of Texas Instruments.
I2C Bus is a registered trademark of Koninklijke Philips Electronics N.V.
Windows is a registered trademark of Microsoft Corporation in the United States and/or other countries.
All trademarks are the property of their respective owners.
1.3
Description
The TMS320C64x+ DSPs (including the TMS320DM647/TMS320DM648 devices) are the highest-
performance fixed-point DSP generation in the TMS320C6000 DSP platform. The DM647, DM648
devices are based on the third-generation high-performance, advanced VelociTI very-long-instruction-
word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice
for digital media applications. The C64x+ devices are upward code-compatible from previous devices
that are part of the C6000 DSP platform. The C64x DSPs support added functionality and have an
expanded instruction set from previous devices.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and
C64x+ CPU, respectively.
With performance of up to 8800 million instructions per second (MIPS) at a clock rate of 1.1 GHz, the
C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses
the operational flexibility of high-speed controllers and the numerical capability of array processors. The
C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly
independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The
eight functional units include instructions to accelerate the performance in video and imaging applications.
The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for up to 4400 million MACs
per second (MMACS), or eight 8-bit MACs per cycle for up tp 8800 MMACS. For more details on the
C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature
number SPRU732).
The devices also have application-specific hardware logic, on-chip memory, and additional on-chip
peripherals similar to the other C6000 DSP platform devices. The core uses a two-level cache-based
architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data
cache (L1D) is a 256K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 4M-
bit (DM648) or 2M-bit (DM647) memory space that is shared between program and data space. L2
memory can be configured as mapped memory, cache, or combinations of the two.
The peripheral set includes five configurable 16-bit video port peripherals (VP0, VP1, VP2, VP3, and
VP4). These video port peripherals provide a glueless interface to common video decoder and encoder
devices. The video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-
BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M), a VCXO interpolated control port (VIC); a 1000
Mbps Ethernet Switch Subsystem with a management data input/output (MDIO) module and two SGMII
2
Features
Copyright 2007–2012, Texas Instruments Incorporated
Product Folder Link(s): TMS320DM647 TMS320DM648
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參數(shù)描述
TMS320DM648ZUTA6 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Digital Media Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320DM648ZUTA8 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Digital Media Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320DM648ZUTD1 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Digital Media Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320DM648ZUTD7 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Digital Media Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
TMS320DM648ZUTD9 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC Digital Media Proc RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT