參數(shù)資料
型號(hào): TMS320C6454ZTZ7
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Fixed-Point Digital Signal Processor
中文描述: 定點(diǎn)數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 120/225頁(yè)
文件大?。?/td> 1663K
代理商: TMS320C6454ZTZ7
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P
7.6.7
Reset Electrical Data/Timing
TMS320C6454
Fixed-Point Digital Signal Processor
SPRS311A–APRIL 2006–REVISED DECEMBER 2006
NOTE
If a configuration pin must be routed out from the device and 3-stated (not driven), the
internal pullup/pulldown (IPU/IPD) resistor should not be relied upon; TI recommends the
use
of
an
external
pullup/pulldown
resistor.
pullup/pulldown resistors and situations where external pullup/pulldown resistors are
required, see
Section 3.7
,
Pullup/Pulldown Resistors
.
For
more
detailed
information
on
Table 7-14. Timing Requirements for Reset
(1)(2)(3)
(see
Figure 7-8
and
Figure 7-9
)
-720
-850
-1000
MIN
256D
(4)
24C
NO.
UNIT
MAX
5
6
t
w(POR)
t
w(RESET)
Pulse duration, POR low
Pulse duration, RESET low
Setup time, boot mode and configuration pins valid before POR high or
RESET high
(5)
Hold time, boot mode and configuration pins valid after POR high or
RESET high
(5)
ns
ns
7
t
su(boot)
6P
ns
8
t
h(boot)
6P
ns
(1)
(2)
(3)
C = 1/CLKIN1 clock frequency in ns.
D = 1/CLKIN2 clock frequency in ns.
P = 1/CPU clock frequency in nanoseconds (ns). Note that after power-on reset and warm reset the CPU frequency is equal to the
CLKIN1 frequency divided by three due to the PLL1 controller being reset (see
Section 7.6
,
Reset Controller
).
If CLKIN2 is not used, t
must be measured in terms of CLKIN1 cycles; otherwise, use CLKIN2 cycles.
AEA[19:0], ABA[1:0], and PCI_EN are the boot configuration pins during device reset.
(4)
(5)
Table 7-15. Switching Characteristics Over Recommended Operating Conditions During Reset
(1)
(see
Figure 7-9
)
-720
-850
-1000
MIN
NO.
PARAMETER
UNIT
MAX
9
t
d(PORH-RSTATH)
C = 1/CLKIN1 clock frequency in ns.
Delay time, POR high AND RESET high to RESETSTAT high
15000C
ns
(1)
For
Figure 7-8
, note the following:
Z group consists of: all I/O/Z and O/Z pins, except for Low and High group pins. Pins become high
impedance as soon as their respective power supply has reached normal operating coditions. Pins
remain in high impedance until configured otherwise by their respective peripheral.
Low group consists of: MTXD0/RMTXD0, MTXD1/RMTXD1, MTXD2/RMTXD2, MTXD3/RMTXD3,
MTXD4/RMTXD4, MTXEN/RMTXEN, and ABUSREQ. Pins become low as soon as their respective
power supply has reached normal operating conditions. Pins remain low until configured otherwise by
their respective peripheral.
High group consists of: AHOLD and HRDY/PIRDY. Pins become high as soon as their respective
power supply has reached normal operating conditions. Pins remain high until configured otherwise by
their respective peripheral.
All peripherals must be enable through software following a Power-on Reset; for more details, see
Section 7.6.1
,
Power-on Reset
.
For power-supply sequence requirements, see
Section 7.3.1
,
Power-Supply Sequencing
.
C64x+ Peripheral Information and Electrical Specifications
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