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| 型號： | TMS320C6205GHKA200 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 6/73頁 |
| 文件大小： | 0K |
| 描述： | IC FIXED-POINT DSP 288-BGA |
| 標準包裝： | 90 |
| 系列： | TMS320C62x |
| 類型： | 定點 |
| 接口： | McBSP，PCI |
| 時鐘速率： | 200MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 128kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.50V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 288-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 288-BGA Microstar（16x16） |
| 包裝： | 托盤 |
| 其它名稱： | 296-32744 TMS320C6205GHKA200-ND |
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TMS320C6205
FIXEDPOINT DIGITAL SIGNAL PROCESSOR
SPRS106G OCTOBER 1999 REVISED JULY 2006
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
Signal Descriptions
SIGNAL
TYPE
DESCRIPTION
NAME
NO.
TYPE
DESCRIPTION
CLOCK/PLL
CLKIN
J3
I
Clock Input
CLKOUT2
T19
O
Clock output at half of device speed
DUsed for synchronous memory interface
CLKMODE0
L3
I
Clock mode select 0
DSelects whether the on-chip PLL is used or bypassed. For more details, see the Clock PLL section.
DThe PLL Multiply Factor is selected at boot configuration. For more details, see the EMIF Data
pin descriptions and the clock PLL section.
PLLV
K5
A§
PLL analog VCC connection for the low-pass filter
PLLG
L2
A§
PLL analog GND connection for the low-pass filter
PLLF
L1
A§
PLL low-pass filter connection to external components and a bypass capacitor
JTAG EMULATION
TMS
E17
I
JTAG test-port mode select (features an internal pullup)
TDO
D19
O/Z
JTAG test-port data out
TDI
D18
I
JTAG test-port data in (features an internal pullup)
TCK
D17
I
JTAG test-port clock
TRST
C19
I
JTAG test-port reset (features an internal pulldown)
EMU1
E18
I/O/Z
Emulation pin 1, pullup with a dedicated 20-k
resistor
EMU0
F15
I/O/Z
Emulation pin 0, pullup with a dedicated 20-k
resistor
RESET AND INTERRUPTS
RESET
C3
I
Device reset
NMI
A8
I
Nonmaskable interrupt
DEdge-driven (rising edge)
EXT_INT7
B15
External interrupts
EXT_INT6
C15
I
External interrupts
Edge-driven
EXT_INT5
A16
I
DEdge-driven
DPolarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0])
EXT_INT4
B16
DPolarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0])
IACK
A15
O
Interrupt acknowledge for all active interrupts serviced by the CPU
INUM3
F12
Active interrupt identification number
INUM2
A14
O
Active interrupt identification number
Valid during IACK for all active interrupts (not just external)
INUM1
B14
O
DValid during IACK for all active interrupts (not just external)
DEncoding order follows the interrupt-service fetch-packet ordering
INUM0
C14
DEncoding order follows the interrupt-service fetch-packet ordering
POWER-DOWN STATUS
PD
B18
O
Power-down modes 2 or 3 (active if high)
I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground
PLLV, PLLG, and PLLF are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins.
§ A = Analog Signal (PLL Filter)
For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-k resistor. For boundary scan, pull down EMU1 and EMU0
with a dedicated 20-k
resistor.
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