參數(shù)資料
型號： TMS320AV411
廠商： Texas Instruments, Inc.
英文描述： Digital NTSC/PAL Encoder(數(shù)字NTSC/PAL編碼器)
中文描述： 數(shù)字的NTSC / PAL編碼器（數(shù)字的NTSC / PAL編碼器）
文件頁數(shù)： 17/33頁
文件大?。?/td> 634K
代理商： TMS320AV411
TMS320AV410, TMS320AV411
DIGITAL NTSC/PAL ENCODER
SCSS020B – JULY 1996 – REVISED MAY 1997
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
01H VID1: video mode register1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IPMD
0
0
VBLDIS
HBLDIS
PLLEN
CLKSEL1
CLKSEL0
NOTE: Bit6–bit5 must be set to 0.
IPMD:
Interpolation mode
0 : Interpolation disable (default)
1 : Interpolate Y and RGB signals by 27 or 28.6 MHz up-sampling
VBLDIS:
Disable internal vertical blanking
0 : Enable internal vertical blanking (default)
1 : Disable internal vertical blanking after the equalization pulse
HBLDIS:
Disable internal horizontal blanking
0 : Enable internal horizontal blanking (default)
1 : Disable internal horizontal blanking except for sync period
PLLEN:
Selects enable/disable of PLL circuit
0 : PLL disable (default)
1 : PLL enable
CLKSEL0:
Selects system clock when in NTSC mode
0 : 27 MHz (default)
1 : 28.6 MHz
Don’t care when in PAL mode
CLKSEL1:
Clock select input. Selects system clock as input from OSCIN or CLKBIN. To execute the
selection, clock must be active to OSCIN and/or CLKBIN prior to selection.
0 : Use clock of OSCIN (default).
1 : Use clock of CLKBIN.
If the internal PLL is disabled and the user wishes to switch from OSCIN to the clock generated by the internal
PLL, PLLEN (bit 2) must first be enabled. Once frequency is locked, CLKSEL1 and CLKSEL0 may be modified
to switch the clock selection.
07H VID2: video mode register2
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
0
0
0
0
0
0
ADJ1
ADJ0
ADJ1:
Input phase adjust1
0 : No phase adjust (default)
1 : Invert Cr, Cb capture phase
ADJ0:
Input phase adjust0
0 : No phase adjust (default)
1 : Invert Y and Cr, Cb capture phase
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