參數(shù)資料
型號(hào)： TMS28F400BZT90BDBJE
廠商： Texas Instruments, Inc.
英文描述： 8-BIT/262144 BY 16-BIT BOOT-BLOCK FLASH MEMORIES
中文描述： 8-BIT/262144由16位啟動(dòng)塊閃存
文件頁數(shù)： 9/29頁
文件大小： 404K
代理商： TMS28F400BZT90BDBJE
TMS28F400BZT, TMS28F400BZB
524288 BY 8-BIT/262144 BY 16-BIT
BOOT-BLOCK FLASH MEMORIES
SMJS400E – JUNE 1994 – REVISED JANUARY 1998
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
command state machine operations (continued)
During an erase cycle, the CSM responds to status read and the erase-suspend commands. When the WSM
has completed its task, the WSM status bit (SB7) is set to a logic-high level and the CSM responds to the full
command set. The CSM stays in the current command state until the microprocessor issues another command.
The WSM successfully initiates an erase or program operation only when V
PP
is within its correct voltage range
(V
PPH
). For data protection, it is recommended that RP be held at a logic-low level during a CPU reset.
clear status register
The internal circuitry can set only the V
PP
status bit (SB3), the program status bit (SB4) and the erase status
bit (SB5) of the status register. The clear status-register command (50h) allows the external microprocessor to
clear these status bits and synchronize internal operations. When the status bits are cleared, the device returns
to the read array mode.
read operations
There are three read operations available: read array, read algorithm-selection code, and read status register.
Read array
The array is read by entering the command code FFh on DQ0–DQ7. Control pins E and G must be at a
logic-low level (V
IL
) and W and RP must be at a logic-low level (V
IH
) to read data from the array. Data is
available on DQ0–DQ15 (word-wide mode) or DQ0–DQ7 (byte-wide mode). Any valid address within any
of the blocks selects that block and allows data to be read from the block.
Read algorithm-selection code
Algorithm-selection codes are read by entering command code 90h on DQ0–DQ7. Two bus cycles are
required for this operation. The first bus cycle is used to enter the command code and the second bus cycle
is used to read the device-equivalent code. Control pins E and G must be at a logic-low level (V
IL
) and W and
RP must be at a logic-high level (V
IH
). Two identifier bytes are accessed by toggling A0. The
manufacturer-equivalent code is obtained on DQ0–DQ7 with A0 at a logic-low level (V
IL
). The
device-equivalent code is obtained when A0 is set to a logic-low level (V
IH
). Alternatively, the manufacturer-
and device-equivalent codes can be read by applying V
ID
(nominally 12 V) to A9 and selecting the desired
code by toggling A0 high or low. All other addresses are in the “don’t care” category (see Table 2, Table 4,
and Table 5).
Read status register
The status register is read by entering the command code 70h on DQ0–DQ7. Control pins E and G must be
at a logic-low level (V
IL
) and W and RP must be at a logic-low level (V
IH
). Two bus cycles are required for this
operation: one to enter the command code and a second to read the status register. In a given read cycle, the
status-register contents are updated on the falling edge of E or G, whichever occurs last within the cycle.
boot-block programming/erasing
Should changes to the boot block be required, RP must be set to V
HH
(12 V) and V
PP
must be set to the
programming voltage level (V
PPH
). If an attempt is made to write, erase or erase-suspend the boot block without
RP at V
HH
, an error signal is generated on SB4 (program-status bit) or SB5 (erase-status bit).
A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)
during the second cycle. After writing FFh or FFFFh during the second cycle, the CSM responds only to status
reads. When the WSM status bit (SB7) is set to a logic-low level, signifying termination of the nonprogram
operation, all commands to the CSM become valid again.
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