
TMS28F010B
131072 BY 8-BIT
FLASH MEMORY
SMJS824B – MAY 1995 – REVISED AUGUST 1997
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements–write/erase/program operations
PARAMETER
ALTERNATE
SYMBOL
’28F010B-90
MIN
NOM
’28F010B-10
MIN
NOM
UNIT
MAX
MAX
tc(W)
tc(W)PR
tc(W)ER
th(A)
th(E)
th(WHD)
tsu(A)
tsu(D)
tsu(E)
tsu(VPPEL)
trec(W)
trec(R)
tw(W)
tw(WH)
tr(VPP)
tf(VPP)
Cycle time, write using W
tAVAV
tWHWH1
tWHWH2
tWLAX
tWHEH
tWHDX
tAVWL
tDVWH
tELWL
tVPEL
tWHGL
tGHWL
tWLWH
tWHWL
tVPPR
tVPPF
90
100
ns
μ
s
ms
Cycle time, programming operation
10
10
Cycle time, erase operation
9.5
9.5
10
Hold time, address
40
55
ns
Hold time, E
0
0
ns
Hold time, data valid after W high
10
10
ns
Setup time, address
0
0
ns
Setup time, data
40
50
ns
Setup time, E before W
15
20
ns
μ
s
μ
s
μ
s
ns
Setup time, VPP to E going low
Recovery time, W before read
1
1
6
6
Recovery time, read before W
0
0
Pulse duration, W (see Note 5)
40
60
Pulse duration, W high
20
20
ns
μ
s
μ
s
Rise time, VPP
Fall time, VPP
1
1
1
1
ALTERNATE
SYMBOL
’28F010B 12
’28F010B-12
’28F010B 15
’28F010B-15
PARAMETER
UNIT
MIN
NOM
MAX
MIN
NOM
MAX
tc(W)
tc(W)PR
tc(W)ER
th(A)
th(E)
th(WHD)
tsu(A)
tsu(D)
tsu(E)
tsu(VPPEL)
trec(W)
trec(R)
tw(W)
tw(WH)
tr(VPP)
tf(VPP)
NOTE 5: Rise/fall time
≤
10 ns
Cycle time, write using W
tAVAV
tWHWH1
tWHWH2
tWLAX
tWHEH
tWHDX
tAVWL
tDVWH
tELWL
tVPEL
tWHGL
tGHWL
tWLWH
tWHWL
tVPPR
tVPPF
120
150
ns
μ
s
ms
Cycle time, programming operation
10
10
Cycle time, erase operation
9.5
10
9.5
10
Hold time, address
60
60
ns
Hold time, E
0
0
ns
Hold time, data valid after W high
10
10
ns
Setup time, address
0
0
ns
Setup time, data
50
50
ns
Setup time, E before W
20
20
ns
μ
s
μ
s
μ
s
ns
Setup time, VPP to E low
Recovery time, W before read
1
1
6
6
Recovery time, read before W
0
0
Pulse duration, W (see Note 5)
60
60
Pulse duration, W high
20
20
ns
μ
s
μ
s
Rise time, VPP
Fall time, VPP
1
1
1
1