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參數(shù)資料
| 型號(hào)： | TMS28F002AXY |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 262144 BY 8-BIT/131072 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES |
| 中文描述： | 262144按8-BIT/131072由16位自動(dòng)選擇啟動(dòng)塊閃存 |
| 文件頁數(shù)： | 14/79頁 |
| 文件大小： | 1064K |
| 代理商： | TMS28F002AXY |
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TMS28F002Axy, TMS28F200Axy
262144 BY 8-BIT/131072 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS826D – JANUARY 1996 – REVISED SEPTEMBER 1997
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
read operations (continued)
read algorithm-selection code
Algorithm-selection codes are read by entering command code 90h on DQ0–DQ7. Two bus cycles are
required for this operation: the first to enter the command code and a second to read the device-equivalent
code. Control pins E and G must be at a logic-low level (V
IL
), and W and RP must be at a logic-high level
(V
IH
). Two identifier bytes are accessed by toggling A0. The manufacturer-equivalent code is obtained on
DQ0–DQ7 with A0 at a logic-low level (V
IL
). The device-equivalent code is obtained when A0 is set to a
logic-high level (V
IH
). Alternatively, the manufacturer- and device-equivalent codes can be read by applying
V
ID
(nominally 12 V) to A9 and selecting the desired code by toggling A0 high or low. All other addresses are
“don’t cares” (see Table 4, Table 6, Table 7, and Table 8).
read status register
The status register is read by entering the command code 70h on DQ0–DQ7. Control pins E and G must be
at a logic-low level (V
IL
) and W and RP must be at a logic-high level (V
IH
). Two bus cycles are required for
this operation: one to enter the command code and a second to read the status register. In a given read
cycle, status register contents are updated on the falling edge of E or G, whichever occurs last within the
cycle.
programming operations
There are two CSM commands for programming: program setup and alternate program setup
(see Table 3). After the desired command code is entered, the WSM takes over and correctly sequences the
device to complete the program operation. During this time, the CSM responds only to status reads until the
program operation has been completed, after which all commands to the CSM become valid again. Once a
program command has been issued, the WSM normally cannot be interrupted until the program algorithm is
completed (see Figure 3 and Figure 4).
Taking RP to V
IL
during programming aborts the program operation. During programming, V
PP
must remain in
the appropriate V
PP
voltage range, as shown in the recommended operating conditions table for the product.
Note that different combinations of RP, WP and V
PP
pin voltage levels ensure that data in certain blocks are
secure, and, therefore, cannot be programmed (see Table 2 for a list of combinations). Only 0s are written and
compared during a program operation. If 1s are programmed, the memory cell contents do not change and no
error occurs.
A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)
during the second cycle. After writing all 1s during the second cycle, the CSM responds only to status reads.
When the SB7 is set to a logic-high level, signifying the nonprogram operation is terminated, all commands to
the CSM become valid again.
erase operations
There are two erase operations that can be performed by the TMS28F002Axy and TMS28F200Axy devices:
block-erase and erase-suspend/erase-resume. An erase operation must be used to initialize all bits in an array
block to 1s. After block-erase-confirm is issued, the CSM responds only to status reads or erase-suspend
commands until the WSM completes its task.
block erasure
Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erasure is
accomplished only by blocks; data at single-address locations within the array cannot be erased
individually. The block to be erased is selected by using any valid address within that block. Note that
different combinations of RP, WP, and V
PP
pin voltage levels ensure that data in certain blocks are secure
and, therefore, cannot be erased (see Table 2 for a list of combinations). Block erasure is initiated by a
command sequence to the CSM: block-erase setup (20h) followed by block-erase confirm (D0h) (see
Figure 5). A two-command erase sequence protects against accidental erasure of memory contents.
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