- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382631 > TMP320F2812ZHHS (Texas Instruments, Inc.) TMS320R2811, TMS320R2812 Digital Signal Processors PDF資料下載
參數(shù)資料
| 型號(hào)： | TMP320F2812ZHHS |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | TMS320R2811, TMS320R2812 Digital Signal Processors |
| 中文描述： | TMS320R2811，TMS320R2812數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 32/147頁(yè) |
| 文件大?。?/td> | 2021K |
| 代理商： | TMP320F2812ZHHS |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)當(dāng)前第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)
Functional Overview
32
June 2004
SPRS257
Generally, the priority of memory bus accesses can be summarized as follows:
Highest:
Data Writes (Simultaneous data and program writes cannot occur
on the memory bus.)
Program Writes (Simultaneous data and program writes cannot occur
on the memory bus.)
Data Reads
Program Reads (Simultaneous program reads and fetches cannot occur
on the memory bus.)
Lowest:
Fetches
(Simultaneous program reads and fetches cannot occur
on the memory bus.)
3.2.3
Peripheral Bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, R281x
adopts a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the
various busses that make up the processor “Memory Bus” into a single bus consisting of 16 address lines and
16 or 32 data lines and associated control signals. Two versions of the peripheral bus are supported on R281x.
One version only supports 16-bit accesses (called peripheral frame 2) and this retains compatibility with
C240x-compatible peripherals. The other version supports both 16- and 32-bit accesses (called peripheral
frame 1).
3.2.4
Real-Time JTAG and Analysis
R281x implements the standard IEEE 1149.1 JTAG interface. Additionally, R281x supports real-time mode
of operation whereby the contents of memory, peripheral and register locations can be modified while the
processor is running and executing code and servicing interrupts. The user can also single step through
non-time critical code while enabling time-critical interrupts to be serviced without interference. R281x
implements the real-time mode in hardware within the CPU. This is a unique feature to R281x, no software
monitor is required. Additionally, special analysis hardware is provided which allows the user to set hardware
breakpoint or data/address watch-points and generate various user selectable break events when a match
occurs.
3.2.5
External Interface (XINTF) (2812 Only)
This asynchronous interface consists of 19 address lines, 16 data lines, and three chip-select lines. The
chip-select lines are mapped to five external zones, Zones 0, 1, 2, 6, and 7. Zones 0 and 1 share a single
chip-select; Zones 6 and 7 also share a single chip-select. Each of the five zones can be programmed with
a different number of wait states, strobe signal setup and hold timing and each zone can be programmed for
extending wait states externally or not. The programmable wait-state, chip-select and programmable strobe
timing enables glueless interface to external memories and peripherals.
3.2.6
M0, M1 SARAMs
All C28x devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer
points to the beginning of block M1 on reset. The M0 block overlaps the 240x device B0, B1, B2 RAM blocks
and hence the mapping of data variables on the 240x devices can remain at the same physical address on
C28x devices. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both
program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The
partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer.
This makes for easier programming in high-level languages.
3.2.7
L0, L1, L2, L3, H0 SARAMs
R281x contains an additional 18K x 16 of single-access RAM (SARAM), divided into 5 blocks (4K + 4K +1K
+1K+ 8K). Each block can be independently accessed, minimizing pipeline stalls. Each block is mapped to
both program and data space.
A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMP320R2811PBKA | TMS320R2811, TMS320R2812 Digital Signal Processors |
| TMP320R2811PGFA | TMS320R2811, TMS320R2812 Digital Signal Processors |
| TMS-WINTOTAL-SWARE | SOFTWARE TMS MARKER |
| TMS1000NC | 4-Bit Microcontroller |
| TMS1200NC | 4-Bit Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP320LBC57PBK80 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
| TMP320LC2401APAGA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS |
| TMP320LC2401APAGS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS |
| TMP320LC2401APGA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS |
| TMP320LC2401APGEA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。