參數(shù)資料
型號: TMP320F2812ZHHS
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述: TMS320R2811,TMS320R2812數(shù)字信號處理器
文件頁數(shù): 110/147頁
文件大?。?/td> 2021K
代理商: TMP320F2812ZHHS
Electrical Specifications
110
June 2004
SPRS257
20
15
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
19
16
14
13
12
SPISTE
In the slave mode, the SPISTE signal should be asserted low at least 0.5t
c(SPC)
before the valid SPI clock edge and remain
low for at least 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 6
23. SPI Slave Mode External Timing (Clock Phase = 0)
A
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