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參數(shù)資料
| 型號(hào)： | TMP320F28044ZGMS |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processor |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 74/107頁(yè) |
| 文件大?。?/td> | 784K |
| 代理商： | TMP320F28044ZGMS |
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6.4.1
Reducing Current Consumption
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
Since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption
can be achieved by turning off the clock to any peripheral module that is not used in a given application.
Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current
consumption even further.
Table 6-2
indicates the typical reduction in current consumption achieved by
turning off the clocks.
Table 6-2. Typical Current Consumption by Various
Peripherals (at 100 MHz)
(1)
PERIPHERAL
MODULE
ADC
I
2
C
ePWM
SCI
SPI
I
CURRENT
REDUCTION (mA)
8
(2)
5
5
4
5
(1)
All peripheral clocks are disabled upon reset. Writing to/reading
from peripheral registers is possible only after the peripheral clocks
are turned on.
This number represents the current drawn by the digital portion of
the ADC module. Turning off the clock to the ADC module results in
the elimination of the current drawn by the analog portion of the
ADC (I
DDA18
) as well.
(2)
NOTE
I
DDIO
current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
NOTE
The baseline I
current (current when the core is executing a dummy loop with no
peripherals enabled) is 110 mA, typical. To arrive at the I
DD
current for a given application,
the current-drawn by the peripherals (enabled by that application) must be added to the
baseline I
DD
current.
74
Electrical Specifications
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