參數(shù)資料
型號: TMP320C6413ZTSA400
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processors
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 62/140頁
文件大?。?/td> 1958K
代理商: TMP320C6413ZTSA400
Terminal Functions
62
April 2004
Revised May 2005
SPRS247E
Table 3
9. Terminal Functions (Continued)
NAME
DESCRIPTION
IPD/
IPU
TYPE
NO.
MCASP1
HCNTL0/AFSR1[1]
Y6
Host control
selects between control, address, or data registers (
I
) [default] or
McASP1 receive frame sync input 1 (
I
).
HHWIL/AFSR1[2]
Y7
I
IPU
Host half-word select
first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (
I
) [default] oror McASP1 receive frame sync
input 2 (
I
) .
HR/W/AFSR1[3]
HAS/ACLKR1[1]
HCS/ACLKR1[2]
HDS1/ACLKR1[3]
AA5
Y5
AA11
AB11
Host read or write select (
I
) [default] or McASP1 receive frame sync input 3 (
I
).
Host address strobe (
I
) [default] or McASP1 receive clock input 1 (
I
).
Host chip select (
I
) [default] or McASP1 receive clock input 2 (
I
).
Host data strobe 1 (
I
) [default] or McASP1 receive clock input 3 (
I
).
HD27/AHCLKX1
Y4
I/O/Z
IPU
Host-port data pin 27 (
I/O/Z
) [default] or McASP1 transmit high-frequency master clock
(
I/O/Z
).
HD22/AFSX1
AB5
I/O/Z
IPU
Host-port data pin 22 (
I/O/Z
) [default] or McASP1 transmit frame sync or left/right clock
(LRCLK) (
I/O/Z
) .
HD24/ACLKX1
AA4
I/O/Z
IPU
Host-port data pin 24 (
I/O/Z
) [default] or McASP1 transmit bit clock (
I/O/Z
).
HD28/AMUTE1
W10
I/O/Z
IPU
Host-port data pin 28 (
I/O/Z
) [default] or McASP1 mute output (
I/O/Z
).
HD29/AMUTEIN1
W11
I
IPU
Host-port data pin 29 (
I/O/Z
) [default] or McASP1 mute input (
I
).
HD26/AHCLKR1
AB4
I/O/Z
IPU
Host-port data pin 26 (
I/O/Z
) [default] or McASP1 receive high-frequency master clock
(
I/O/Z
).
HD23/AFSR1
AB9
I/O/Z
IPU
Host-port data pin 23 (
I/O/Z
) [default] or McASP1 receive frame sync or left/right clock
(LRCLK) (
I/O/Z
).
HD25/ACLKR1
AA9
I/O/Z
IPU
Host-port data pin 25 (
I/O/Z
) [default] or McASP1 receive bit clock (
I/O/Z
).
HD21/AXR1[5]
HD20/AXR1[4]
HD19/AXR1[3]
HD18/AXR1[2]
HD17/AXR1[1]
HD16/AXR1[0]
Y9
AB8
AA6
AB7
AA7
AB6
I/O/Z
IPU
Host port data pins [21:16] (
Host-port data pins [21:16] (
I/O/Z
) [default] or McASP1 TX/RX data pins [5:0] (
I/O/Z
).
HOST-PORT INTERFACE (HPI)
HINT
AA8
O/Z
IPU
Host interrupt from DSP to host (
O
)
HCNTL1
W7
I
IPU
Host control
selects between control, address, or data registers (
I
)
HCNTL0/AFSR1[1]
Y6
Host control
selects between control, address, or data registers (
I
) [default] or
McASP1 receive frame sync input 1 (
I
).
HHWIL/AFSR1[2]
Y7
I
IPU
Host half-word select
first or second half-word (not necessarily high or low order)
[For HPI16 bus width selection only] (
I
) [default] or McASP1 receive frame sync
input 2 (
I
).
HR/W/AFSR1[3]
HAS/ACLKR1[1]
HCS/ACLKR1[2]
HDS1/ACLKR1[3]
AA5
Y5
AA11
AB11
Host read or write select (
I
) [default] or McASP1 receive frame sync input 3 (
I
).
Host address strobe (
I
) [default] or McASP1 receive clock input 1 (
I
).
Host chip select (
I
) [default] or McASP1 receive clock input 2 (
I
).
Host data strobe 1 (
I
) [default] or McASP1 receive clock input 3 (
I
).
HDS2
AB12
I
IPU
Host data strobe 2 (
I
)
HRDY
I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog Signal
IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k
IPD or IPU resistor. To pull up a signal to the opposite
supply rail, a 1-k
resistor should be used.)
§
These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
Y10
O/Z
IPU
Host ready from DSP to host (
O
)
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