參數(shù)資料
型號: TMP320C6413ZTS500
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processors
中文描述: 定點(diǎn)數(shù)字信號處理器
文件頁數(shù): 96/140頁
文件大?。?/td> 1958K
代理商: TMP320C6413ZTS500
Input and Output Clocks
96
April 2004
Revised May 2005
SPRS247E
Table 7
7. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the
EMIFA Module
(see Figure 7
6)
NO.
PARAMETER
400
500
UNIT
MIN
MAX
NE + 0.7
0.5NE + 0.7
0.5NE + 0.7
1
2
3
4
5
6
t
c(EKO2)
t
w(EKO2H)
t
w(EKO2L)
t
t(EKO2)
t
d(EKIH-EKO2H)
t
d(EKIH-EKO2L)
Cycle time, AECLKOUT2
Pulse duration, AECLKOUT2 high
Pulse duration, AECLKOUT2 low
Transition time, AECLKOUT2
Delay time, ECLKIN high to AECLKOUT2 high
Delay time, ECLKIN high to AECLKOUT2 low
NE
0.7
0.5NE
0.7
0.5NE
0.7
ns
ns
ns
ns
ns
ns
1
8
8
1
1
The reference points for the rise and fall transitions are measured at V
OL
MAX and V
OH
MIN.
E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA.
N = the EMIF input clock divider; N = 1, 2, or 4.
5
6
AECLKIN
AECLKOUT2
3
2
4
4
1
Figure 7
6. AECLKOUT2 Timing for the EMIFA Module
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