參數(shù)資料
型號(hào): TMP320C6413ZTS500
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Fixed-Point Digital Signal Processors
中文描述: 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù): 106/140頁
文件大?。?/td> 1958K
代理商: TMP320C6413ZTS500
Synchronous DRAM Timing
106
April 2004
Revised May 2005
SPRS247E
AECLKOUTx
ACEx
ABE[3:0]
AEA[12:3]
AED[31:0]
AAOE/ASDRAS/ASOE
AARE/ASDCAS/ASADS/
ASRE
AAWE/ASDWE/ASWE
AEA13
AEA[22:14]
BE1
BE2
BE3
BE4
Bank
Column
D1
D2
D3
D4
11
8
9
5
5
5
4
2
11
8
9
4
4
2
1
10
3
4
WRITE
PDT
14
14
AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, and AAOE/ASDRAS/ASOE operate as AsDCAS, ASDWE, and ASDRAS, respectively,
during SDRAM accesses.
PDT signal is only asserted when the EDMA is in PDT mode (set the PDTD bit to 1 in the EDMA options parameter RAM). For PDT write, data
is not driven (in High-Z). The PDTWL field in the PDT control register (PDTCTL) configures the latency of the PDT signal with respect to the data
phase of a write transaction. The latency of the PDT signal for a write transaction can be programmed to 0, 1, 2, or 3 by setting PDTWL to 00,
01, 10, or 11, respectively. PDTWL equals 00 (zero latency) in Figure 7
13.
Figure 7
13. SDRAM Write Command for EMIFA
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