參數(shù)資料
型號: TMP320C6413GTS400
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Fixed-Point Digital Signal Processors
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 15/140頁
文件大小: 1958K
代理商: TMP320C6413GTS400
Functional Block Diagram
15
April 2004
Revised May 2005
SPRS247E
2.3.1
Functional Block Diagram
Figure 2
2 shows the functional block diagram of the C6413/C6410 device.
Test
C64x DSP Core
Data Path B
B Register File
B31
B16
B15
B0
Instruction Fetch
Instruction Dispatch
Advanced Instruction Packet
Instruction Decode
Data Path A
A Register File
A31
A16
A15
A0
Power-Down
Logic
.L1
.S1
.M1 .D1
.D2
.M2
.S2
.L2
32
SDRAM
FIFO
SBSRAM
SRAM
L1P Cache
Direct-Mapped
16K Bytes Total
Control
Registers
Control
Logic
L1D Cache 2-Way Set-Associative
16K Bytes Total
Advanced
In-Circuit
Emulation
Interrupt
Control
TMS320C6413/C6410
Enhanced
DMA
Controller
(edma)
L2
Cache
Memory
256KBytes
§
OSCILLATOR
and PLL
(x1, x5
x12, x16,
x18, x19
x22, x24)
Timer 2
EMIF A
ZBT SRAM
Timer 1
Boot Configuration
ROM/FLASH
I/O Devices
McBSP0
GP0
16
Timer 0
McBSP1
McASP0
and
or
HPI32
HPI16
McASP1
McBSPs: Framing Chips
H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs
GP0[15:8] pins are muxed with the HPI HD[15:8] pins and GP0[2:1] pins are muxed with CLKOUT6 and CLKOUT4,
respectively.
§
Note: the C6413 device has 256K-Bytes L2 Cache Memory; the C6410 device has
only
128K-Bytes L2 Cache Memory.
I2C0
I2C1
Figure 2
2. Functional Block Diagram
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