參數(shù)資料
型號(hào)： TMP320C6413GTS400
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： Fixed-Point Digital Signal Processors
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 100/140頁
文件大?。?/td> 1958K
代理商： TMP320C6413GTS400
Programmable Synchronous Interface Timing
100
April 2004
Revised May 2005
SPRS247E
7.3
Programmable Synchronous Interface Timing
Table 7
10. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module
(see Figure 7
9)
NO.
400
500
UNIT
MIN
3.1
1.5
MAX
6
7
t
su(EDV-EKOxH)
t
h(EKOxH-EDV)
Setup time, read AEDx valid before AECLKOUTx high
Hold time, read AEDx valid after AECLKOUTx high
ns
ns
Table 7
11. Switching Characteristics Over Recommended Operating Conditions for Programmable
Synchronous Interface Cycles for EMIFA Module
(see Figure 7
9
Figure 7
11)
NO.
PARAMETER
400
500
UNIT
MIN
1.3
MAX
6.4
6.4
1
2
3
4
5
8
9
10
11
12
t
d(EKOxH-CEV)
t
d(EKOxH-BEV)
t
d(EKOxH-BEIV)
t
d(EKOxH-EAV)
t
d(EKOxH-EAIV)
t
d(EKOxH-ADSV)
t
d(EKOxH-OEV)
t
d(EKOxH-EDV)
t
d(EKOxH-EDIV)
t
d(EKOxH-WEV)
Delay time, AECLKOUTx high to ACEx valid
Delay time, AECLKOUTx high to ABEx valid
Delay time, AECLKOUTx high to ABEx invalid
Delay time, AECLKOUTx high to AEAx valid
Delay time, AECLKOUTx high to AEAx invalid
Delay time, AECLKOUTx high to ASADS/ASRE valid
Delay time, AECLKOUTx high to, ASOE valid
Delay time, AECLKOUTx high to AEDx valid
Delay time, AECLKOUTx high to AEDx invalid
Delay time, AECLKOUTx high to ASWE valid
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.3
6.4
1.3
1.3
1.3
6.4
6.4
6.4
1.3
1.3
6.4
The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):
Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency
Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency
ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has been issued
(CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).
Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect cycles
(RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).
Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2
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