SPRS196H MARCH 2002 REVISED JULY 2004
101
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
timing requirements for serial EEPROM interface (see Figure 50)
NO.
300
UNIT
MIN
MAX
8
tsu(DIV-CLKH)
th(CLKH-DIV)
Setup time, XSP_DI valid before XSP_CLK high
50
ns
9
Hold time, XSP_DI valid after XSP_CLK high
0
ns
switching characteristics over recommended operating conditions for serial EEPROM interface
(see Figure 50)
NO.
PARAMETER
300
NOM
UNIT
MIN
MAX
1
tw(CSL)
td(CLKL-CSL)
td(CSH-CLKH)
tw(CLKH)
tw(CLKL)
tosu(DOV-CLKH)
toh(CLKH-DOV)
Pulse duration, XSP_CS low
4092P
ns
2
Delay time, XSP_CLK low to XSP_CS low
0
ns
3
Delay time, XSP_CS high to XSP_CLK high
2046P
ns
4
Pulse duration, XSP_CLK high
2046P
ns
5
Pulse duration, XSP_CLK low
2046P
ns
6
Output setup time, XSP_DO valid before XSP_CLK high
2046P
ns
7
Output hold time, XSP_DO valid after XSP_CLK high
2046P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
8
7
6
3
2
5
4
1
XSP_CS
XSP_CLK
XSP_DO
XSP_DI
9
Figure 50. PCI Serial EEPROM Interface Timing