- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383960 > TMP320C6411AGLZ (Texas Instruments, Inc.) Toggle Switch; Circuitry:SPDT; Switch Operation:On-None-(On); Contact Current Max:5A; Switch Terminals:Solder Lug; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes PDF資料下載
參數(shù)資料
| 型號： | TMP320C6411AGLZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Toggle Switch; Circuitry:SPDT; Switch Operation:On-None-(On); Contact Current Max:5A; Switch Terminals:Solder Lug; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | 定點(diǎn)數(shù)字信號處理器 |
| 文件頁數(shù)： | 91/119頁 |
| 文件大小： | 1742K |
| 代理商： | TMP320C6411AGLZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁當(dāng)前第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁
SPRS196H MARCH 2002 REVISED JULY 2004
91
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
RESET TIMING
timing requirements for reset
(see Figure 37)
NO.
300
UNIT
MIN
10P
MAX
1
tw(RST)
Width of the RESET pulse (PLL stable)
Width of the RESET pulse (PLL needs to sync up)§
Setup time, boot configuration bits valid before RESET high
Hold time, boot configuration bits valid after RESET high
Setup time, PCLK active before RESET high||
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x6 when CLKIN and PLL are stable.
§This parameter applies to CLKMODE x6 only (it does not apply to CLKMODE x1). The RESET signal is not connected internally to the clock PLL
circuit. The PLL, however, may need up to 250
μ
s to stabilize following device power up or after PLL configuration has been changed. During
that time, RESET must be asserted to ensure proper device operation. See the
clock PLL
section for PLL lock times.
LEND, BOOTMODE[1:0], ECLKIN_SEL[1:0], EEAI, and HD5/AD5 are the boot configuration pins during device reset.
#E = 1/AECLKIN clock frequency in ns. C = 1/CLKIN clock frequency in ns. Select whichever value is larger for the
MIN
parameter.
||N = the PCI input clock (PCLK) period in ns. When PCI is enabled (PCI_EN = 1), this parameter
must
be met.
ns
μ
s
ns
250
16
tsu(boot)
th(boot)
tsu(PCLK-RSTH)
4E or 4C#
17
4P
ns
18
32N
ns
switching characteristics over recommended operating conditions during reset
(see Figure 37)
NO.
PARAMETER
300
UNIT
MIN
MAX
2
td(RSTL-ECKI)
td(RSTH-ECKI)
td(RSTL-ECKO1HZ)
td(RSTH-ECKO1V)
td(RSTL-EMIFZHZ)
td(RSTH-EMIFZV)
td(RSTL-EMIFHIV)
td(RSTH-EMIFHV)
td(RSTL-EMIFLIV)
td(RSTH-EMIFLV)
td(RSTL-LOWIV)
td(RSTH-LOWV)
td(RSTL-ZHZ)
td(RSTH-ZV)
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.
EMIF Z group consists of:
EA[22:3], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SADS/SRE, AWE/SDWE/SWE, and AOE/SDRAS/SOE,
SOE3, SDCKE, and PDT.
EMIF high group consists of: HOLDA (when the corresponding HOLD input is high)
EMIF low group consists of:
BUSREQ; HOLDA (when the corresponding HOLD input is low)
Low group consists of:
XSP_CS, XSP_CLK, and XSP_DO; all of which apply only when PCI EEPROM (EEAI) is enabled
(with PCI_EN = 1). Otherwise, the XSP_CLK and XSP_DO pins are in the Z group. For more details
on the PCI configuration pins, see the Device Configurations section of this data sheet.
Z group consists of:
HD[31:0]/AD[31:0], CLKX0, CLKX1, XSP_CLK, FSX0, FSX1, DX0, DX1, XSP_DO, CLKR0, CLKR1,
FSR0, FSR1, TOUT0, TOUT1, GP[8:0], GP10/PCBE3, HR/W/PCBE2, HDS2/PCBE1, PCBE0,
GP13/PINTA, GP11/PREQ, HDS1/PSERR, HCS/PPERR, HCNTL1/PDEVSEL, HAS/PPAR,
HCNTL0/PSTOP, HHWIL/PTRDY (16-bit HPI mode only), HRDY/PIRDY, and HINT/PFRAME.
Delay time, RESET low to ECLKIN synchronized internally
2E
3P + 20E
ns
3
Delay time, RESET high to ECLKIN synchronized internally
2E
8P + 20E
ns
4
Delay time, RESET low to ECLKOUT1 high impedance
2E
ns
5
Delay time, RESET high to ECLKOUT1 valid
8P + 20E
ns
6
Delay time, RESET low to EMIF Z high impedance
2E
3P + 4E
ns
7
Delay time, RESET high to EMIF Z valid
16E
8P + 20E
ns
8
Delay time, RESET low to EMIF high group invalid
2E
ns
9
Delay time, RESET high to EMIF high group valid
8P + 20E
ns
10
Delay time, RESET low to EMIF low group invalid
2E
ns
11
Delay time, RESET high to EMIF low group valid
8P + 20E
ns
12
Delay time, RESET low to low group invalid
0
ns
13
Delay time, RESET high to low group valid
11P
ns
14
Delay time, RESET low to Z group high impedance
0
ns
15
Delay time, RESET high to Z group valid
2P
8P
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMP32C6411ZLZ | FIXED POINT DIGITAL SIGNAL PROCESSOR |
| TMS32C6411AGLZ | FIXED POINT DIGITAL SIGNAL PROCESSOR |
| TMS32C6411AZLZ | FIXED POINT DIGITAL SIGNAL PROCESSOR |
| TMS32C6411GLZ | FIXED POINT DIGITAL SIGNAL PROCESSOR |
| TMS32C6411ZLZ | FIXED POINT DIGITAL SIGNAL PROCESSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMP320C6411AZLZ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6411GLZ | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED POINT DIGITAL SIGNAL PROCESSOR |
| TMP320C6411GLZ300 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMP320C6411GLZ5E0 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| TMP320C6411GLZA300 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:FIXED-POINT DIGITAL SIGNAL PROCESSORS |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。