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| 型號(hào)： | TMP320C6411AGLZ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Toggle Switch; Circuitry:SPDT; Switch Operation:On-None-(On); Contact Current Max:5A; Switch Terminals:Solder Lug; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes RoHS Compliant: Yes |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 103/119頁(yè) |
| 文件大?。?/td> | 1742K |
| 代理商： | TMP320C6411AGLZ |
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SPRS196H MARCH 2002 REVISED JULY 2004
103
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
MULTICHANNEL BUFFERED SERIAL PORT (McBSP) TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP
(see Figure 51)
NO.
PARAMETER
300
MIN
UNIT
MAX
1
td(CKSH-CKRXH)
Delay time, CLKS high to CLKR/X high for internal CLKR/X generated
from CLKS input
1.4
10
ns
2
tc(CKRX)
tw(CKRX)
td(CKRH-FRV)
Cycle time, CLKR/X
CLKR/X int
4P or 6.67§#
ns
3
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X int
C 1||
C + 1||
ns
4
Delay time, CLKR high to internal FSR valid
CLKR int
2.1
3
ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int
1.7
3
ns
CLKX ext
1.7
9
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last
data bit from CLKX high
CLKX int
3.9
4
ns
CLKX ext
2.0
9
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int
3.9 + D1
4 + D2
ns
CLKX ext
2.0 + D1
9 + D2
14
td(FXH-DXV)
Delay time, FSX high to DX valid
FSX int
2.3 + D1
5.6 + D2
ns
ONLY applies when in data
delay 0 (XDATDLY = 00b) mode
FSX ext
1.9 + D1
9 + D2
CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
Minimum delay times also represent minimum output hold times.
§Minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing
requirements.
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
#Use whichever value is greater.
||C =
H or L
S =
sample rate generator input clock = 4P if CLKSM = 1 (P = 1/CPU clock frequency)
=
sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H =
CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L =
CLKX low pulse width
= (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see footnote above).
Extra delay from CLKX high to DX valid applies
only
to the first data bit of a device, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
Extra delay from FSX high to DX valid
applies
only
to the first data bit of a device
, if and only if DXENA = 1 in SPCR.
if DXENA = 0, then D1 = D2 = 0
if DXENA = 1, then D1 = 4P, D2 = 8P
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