參數(shù)資料
型號(hào): TMDS461PZTR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: PLASTIC, TQFP-100
文件頁(yè)數(shù): 14/43頁(yè)
文件大小: 3111K
代理商: TMDS461PZTR
VCC
50 W
D+
D-
VD+ VID
Y
Z
VY
VZ
50 W
VD-
2
V
=V
-V
V
=(V
+V )
ID
D+
D-
ICM
D+
D-
2
V
=V -V
V
=(V +V )
OD
Y
Z
OC
Y
Z
0.5pF
50 W
AVCC
www.ti.com ............................................................................................................................................................................................... SLLS915 – JANUARY 2009
SWITCHING CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX
UNIT
tJITC(PP)
Peak-to-peak output residual clock jitter
AVCC = 3.3 V, RT = 50 , input TMDS clock
10
35
ps
frequency = 225 MHz. See Figure 18 for
measurement setup; residual jitter is the total
jitter measured at TTP4 minus the jitter
measured at TTP1. See Figure 19 for the loss
profile of the cable used for tJITC(PP)
measurement.
tCLK1
Valid clock-detect enable time
AVCC = 3.3 V, RT = 50 , input TMDS clock
300
500
ns
frequency = 300 MHz. See Figure 17.
tCLK2
Invalid clock-detect disable time
AVCC = 3.3 V, RT = 50 , input TMDS clock
500
800
ns
frequency = 1 MHz. See Figure 17.
tSEL1
Port selection time (see (4)
AVCC = 3.3 V, RT = 50
300
500
ns
tSEL2
Port deselection time (see (5))
AVCC = 3.3 V, RT = 50
40
50
ns
fCD
Clock-detect frequency
AVCC = 3.3 V, RT = 50 . See Figure 17.
25
300
MHz
(4)
tSEL1 includes the time for the valid clock detect enable time and tS1(HPD), because the tS1(HPD) event happens in parallel with tSEL1; thus,
the tSEL1 time is primarily the tCLK1 time.
(5)
tSEL2 is primarily the tS2(HPD) time.
Figure 13. TMDS Main Link Test Circuit
Copyright 2009, Texas Instruments Incorporated
21
Product Folder Link(s) :TMDS461
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