- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄384014 > TMC2491A (Fairchild Semiconductor Corporation) Multistandard Digital Video Encoder(多標(biāo)準(zhǔn)數(shù)字視頻編碼器) PDF資料下載
參數(shù)資料
| 型號(hào)： | TMC2491A |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | Multistandard Digital Video Encoder(多標(biāo)準(zhǔn)數(shù)字視頻編碼器) |
| 中文描述： | 多標(biāo)準(zhǔn)數(shù)字視頻編碼器（多標(biāo)準(zhǔn)數(shù)字視頻編碼器） |
| 文件頁(yè)數(shù)： | 22/36頁(yè) |
| 文件大?。?/td> | 208K |
| 代理商： | TMC2491A |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)當(dāng)前第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)
TMC2490A/TMC2491A
PRODUCT SPECIFICATION
22
Closed Caption Insertion
The TMC2490(1)A includes a flexible closed caption pro-
cessor. It may be programmed to insert a closed caption sig-
nal on any line within a range of 16 lines on ODD and/or
EVEN fields.
Closed Caption insertion overrides all other configurations
of the encoder. If it is specified on an active video line, it
takes precedence over the video data and removes NTSC
setup if setup has been programmed for the active video
lines.
Closed Caption Control
Closed caption is turned on by setting CCON HIGH. When-
ever the encoder begins producing a line specified by
CCFLD and CCLINE, it will insert a closed caption line in
its place. If CCRTS is HIGH, the data contained in CCDx
will be sent. IF CCRTS is LOW, Null Bytes (hex 00 with
ODD parity) will be sent.
Line Selection
The line to contain CC data is selected by a combination of
the CCFLD bit and the CCLINE bits. CCLINE is added to
the offset shown in Table 13 to specify the line.
Table 13. Closed Caption Line Selection
Parity Generation
Standard Closed-Caption signals employ ODD parity, which
may be automatically generated by setting CCPAR HIGH.
Alternatively, parity may be generated externally as part of
the bytes to be transmitted, and, with CCPAR LOW, the
entire 16 bits loaded into the CCDx registers will be sent
unchanged.
Operating Sequence
A typical operational sequence for closed-caption insertion
on Line 21 is:
1.
Read Register 22 and check that bit 6 is LOW, indicat-
ing that the CCDx registers are ready to accept data.
2.
If ready, write two bytes of CC data into registers 20 and
21.
Standard
525
Offset
12
274
9
321
Field
ODD
EVEN
ODD
EVEN
Lines
12-27
274-289
9-24
321-336
625
3.
Write into register 22 the proper combination of CCFLD
and CCLINE. CCPAR may be written as desired. Set
CCRTS HIGH.
4.
The CC data is transmitted during the specified line.
As soon as CCDx is transferred into the CC processor (and
CCRTS goes LOW), new data may be loaded into registers
20 and 21. This allows the user to transmit CC data on sev-
eral consecutive lines by loading data for line n+1 while data
is being sent on line n.
Registers 20-21 auto-increment when read or written. Regis-
ter 22 does not. The microcontroller can repeatedly read
register 22 until CCRTS is found to be LOW, then address
register 20 and write three auto-incremented bytes to set up
for the next CC line.
Parallel Microprocessor Interface
The parallel microprocessor interface, active when SER is
HIGH, employs an 11-line interface, with an 8-bit data bus
and one address bit: two addresses are required for device
programming and pointer-register management. Address bit
0 selects between reading/writing the register addresses and
reading/writing register data. When writing, the address is
presented along with a LOW on the R/W pin during the fall-
ing edge of CS. Eight bits of data are presented on D
7-0
dur-
ing the subsequent rising edge of CS.
In read mode, the address is accompanied by a HIGH on the
R/W pin during a falling edge of CS. The data output pins go
to a low-impedance state t
DOZ
ns after CS falls. Valid data is
present on D
7-0
t
DOM
after the falling edge of CS.
Table 14. Parallel Port Control
ADR
1
R/W
0
Action
Load D
7-0
into Control Register
pointer.
Read Control Register pointer on
D
7-0
.
Write D
7-0
to addressed Control
Register.
Read addressed Control Register
on D
7-0
.
1
1
0
0
0
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMCREOJ156KTR | Low ESR Tantalum Chip Capacitors |
| TMCR | Low ESR Tantalum Chip Capacitors |
| TMCRB1A106KTR | Low ESR Tantalum Chip Capacitors |
| TMCRB1A106MTR | Low ESR Tantalum Chip Capacitors |
| TMCRB1A107KTR | Low ESR Tantalum Chip Capacitors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC249A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Current Microstep Stepper Motor Driver with sensorless stall detection, protection / diagnostics and SPI Interface |
| TMC249-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:High Current Microstep Stepper Motor Driver with Sensorless Stall D e t e c t i o n ,P rotection / Diagnosis and SPI Interface |
| TMC249A-LA | 制造商:Trinamic 功能描述:IC BRIDGE DRIVER SPI/ANLG 32QFN |
| TMC249A-SA | 制造商:Trinamic 功能描述:STEPPER MOTOR DRIVER SMD SO-28 制造商:Trinamic 功能描述:STEPPER MOTOR DRIVER, SMD, SO-28 制造商:Trinamic 功能描述:IC MOTOR DRIVER, FULL BRIDGE, 1mA SOIC-28; Motor Type:Full Bridge; No. of Outputs:8; Output Current:1mA; Output Voltage:34V; Driver Case Style:SOIC; No. of Pins:28; Supply Voltage Min:3V; Supply Voltage Max:5.5V; MSL:MSL 2 - 1 year ;RoHS Compliant: Yes |
| TMC249-EVAL | 制造商:Trinamic 功能描述:EVALUATION BOARD FOR TMC249 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。