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參數(shù)資料
| 型號(hào)： | TMC2360KLC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL ENCODER, PQFP80 |
| 封裝： | 2.70 MM HEIGHT, MQFP-80 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 158K |
| 代理商： | TMC2360KLC |
PRODUCT SPECIFICATION
TMC2360
7
Clocks
There are three internal clocks, ADCLK, PXCK, and
27MHz. ADCLK is the clock for the A/D converters with
sampling on the edge selected by PHASE. PXCK is the
encoder clock for sequencing data to the D/A converters at a
2X rate. 27MHz is the reference clock from which the
chroma subcarrier data is synthesized.
ADCLK and PXCK clocks may be derived from internal or
external phase-locked loops. Only an external controller con-
taining the phase detector, charge pump, and VCO is needed
for each loop. An internal divider programmed with the cor-
rect counts is included within the TMC2360.
Control of the internal/external PLL modes is either via the
A0 and A1 pins (see Table 1) or through the VGA1 Control
register, which can be programmed via the microprocessor
port.
With control via A0 and A1 pins, the outputs PDIVM and
ADIVN are high impedance unless either PLL is pro-
grammed to be external. A0 and A1 also control the direction
of the ADCLK and PXCK clock pins. Each clock (ADCLK
and PXCK) is an output in the internal mode and an output
in the external mode.
Table 1. Internal/External Phase-locked Loop Selection (MPEN = L)
A1
A0
PLLA
PLLP
ADIVN
PDIVM
ADCLK
PXCK
0
Internal
High-Z
Output
0
1
Internal
External
1/N
1/M
Output
Input
1
0
External
Internal
1/N
1/M
Input
Output
1
External
1/N
1/M
Input
A/D Clock (ADCLK)
ADCLK is the buffered analog-to-digital converter clock
output which is derived from incoming VGA horizontal sync
(VGAHS) by a phase-lock loop (PLL). Either an internal
PLL or an external PLL controller may be selected by pro-
gramming pin A1.
A/D Clock frequency is set by the PLL divide-by-N counter
where N is the number of A/D samples between the horizon-
tal sync pulses in each VGA line.
Pre-programmed values selected by the TVSTD1-0 and
PAL800 control inputs set N and the clock frequency as
shown in Table 2.
Table 2. VGA A/D Clock
For an internal loop, the recommended loop lter to be con-
nected to the LPFA pin is shown in Figure 1.
Figure 1. PLL Low Pass Filter
Pixel Clock (PXCK)
PXCK is the buffered video encoder clock output which is
derived from the incoming VGA HSYNC signal by a second
phase-lock loop. Either an internal PLL or an external PLL
controller may be selected by programming pin A0.
With the internal loop selected, Figure 1 shows the recom-
mended loop lter, which should be connected to LPFP.
Clock frequency is set by the PLL divide-by-M counter. M is
the number of encoder samples between horizontal sync
pulses. Because of 2X oversampling, the pixel rate is twice
the TV square pixel rate. Table 3 shows the video output
clock rates and M values.
Television
Standard
TVSTD1-0 PAL800
ADCLK
Freq. (MHz)
N
NTSC
0x
0
25.175
800
PAL640
10
0
25.250
808
PAL800
10
1
36.000
1152
PALM
11
0
25.175
800
LPF
0.1
F
680pF
29001A
39K
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