參數(shù)資料
型號(hào)： TMC22053A
廠商： Fairchild Semiconductor Corporation
英文描述： 8-Bit Digital Video Decoder(8位數(shù)字視頻譯碼器)
中文描述： 8位數(shù)字視頻解碼器（8位數(shù)字視頻譯碼器）
文件頁(yè)數(shù)： 6/84頁(yè)
文件大?。?/td> 420K
代理商： TMC22053A
TMC22x5yA
PRODUCT SPECIFICATION
6
Pin Descriptions
Pin Name
Inputs
VIDEOA
9-0
Pin Number
Value
Pin Function Description
86, 85, 84, 83,
82, 81, 80, 79,
78, 77
75, 74, 73, 72,
71, 70, 69, 68,
67, 66
49
TTL
Video input A.
An 8 or 10 bit data input to the input multiplexer.
For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOA
9-2
).
VIDEOB
9-0
TTL
Video input B.
An 8 or 10 bit data input to the input multiplexer.
For 8-bit versions (TMC2205yA) the data are left-justified (VIDEOB
9-2
).
VSYNC
TTL
Vertical sync input.
A vertical sync signal (active low) occurring at the
start of the first vertical sync pulse in a vertical field group. A falling edge
of VSYNC which is coincident with a falling edge of HSYNC indicates
field 1. This signal is active only when SPGIP
1-0
= 00.
Horizontal sync input.
A horizontal sync signal (active low) occurring
at the falling edge of the video sync. This signal is active only when
SPGIP
1-0
= 00.
Master decoder control.
HSYNC
48
TTL
MASTER
1-0
88, 87
TTL
00
01
10
11
Control register select.
This signal switches between two sets of
registers which control the gain or hue values in the output matrix.
When BUFFER = 0, registers 17-1F are active. When BUFFER = 1,
registers 27-2F take control.
Master processing clock.
The clock signal can either be at twice the
pixel data rate in the line locked modes, or at four times the subcarrier
frequency in the subcarrier mode. The interpretation of the CLOCK
signal is set by the CKSEL register bit.
Programmable function pin.
The function specified by the SET
register is active when SET is low. The decoder returns to its previous
operation when SET goes high.
Adaptive comb decoder
Simple bandsplit decoder
Reserved
Flat notched luma and simple bandsplit chroma
BUFFER
50
TTL
CLOCK
89
TTL
SET
52
TTL
Outputs
G/Y
9-0
93, 94, 95, 96,
97, 98, 99, 100,
1, 2
6, 7, 8, 9, 10,
11, 12, 13, 14,
15
18, 19, 20, 21,
22, 23, 24, 25,
26, 27
35
TTL
Green or Luminance digital output.
For 8-bit versions (TMC2205yA)
the data are left-justified (G/Y
9-2
).
B/C
B9-0
TTL
Blue or C
B
digital output.
For 8-bit versions (TMC2205y) the data are
left-justified (B/C
B 9-2
).
R/C
R9-0
TTL
Red or C
R
digital output.
For 8-bit versions (TMC2205yA) the data are
left-justified (R/C
R 9-2
).
DVSYNC
TTL
Vertical sync output.
The DVSYNC signal occurs once per field and
lasts for 1 video line.
Horizontal sync output.
The DHSYNC signal occurs once per line and
lasts for 64 clock periods.
Data synchronization output.
LDV can be an internally or externally
generated clock signal. The internal LDV signal is produced when the
CLOCK input is at twice the pixel data rate (PXCK); and is a pixel data
rate clock phase locked to the falling edge of the HSYNC. The external
LDV can be selected under software control, and must be at the
CLOCK, or a sub multiple of the CLOCK, frequency.
DHSYNC
34
TTL
LDV
3
TTL
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