參數資料
型號: TMC22053A
廠商: Fairchild Semiconductor Corporation
英文描述: 8-Bit Digital Video Decoder(8位數字視頻譯碼器)
中文描述: 8位數字視頻解碼器(8位數字視頻譯碼器)
文件頁數: 30/84頁
文件大?。?/td> 420K
代理商: TMC22053A
TMC22x5yA
PRODUCT SPECIFICATION
30
Control Register Definitions
(continued)
Output Format Control (26)
7
6
5
4
3
2
1
0
Reserved
LDVIO
OPCKS
DPCEN
DPC
Reg
26
26
26
Bit
7-6
5
4
Name
Reserved
LDVIO
OPCKS
Description
Reserved, set to zero.
LDV clock select.
LDV is an output when LOW and an input when HIGH
Output clock select.
The output data are clocked by the CLOCK pin when
LOW and by the LDV pin when HIGH.
DPC enable.
When HIGH on the TMC22153A, the Decoder Product Code is
enabled: a value written into DPC determines the decoder product emulated
by the TMC22153A. In all other versions of the decoder, DPC is read-only,
and returns the code of the particular encoder version installed.
Decoder product code
26
3
DPCEN
26
2-0
DPC
Read/Write in the TMC22153A only. Read-only in all other devices.
Buffered register set 1 (27)
Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
SG1
7
SG1
6
SG1
5
SG1
4
SG1
3
SG1
2
SG1
1
SG1
0
Reg
27
Bit
7-0
Name
SG1
7-0
Description
Msync gain, 8 lsbs.
Bottom 8 bits of the mixed sync scalar
lsb = 1/256
Buffered register set 1 (28)
Active when BUFFER pin set HIGH.
7
6
5
4
3
2
1
0
YG1
7
YG1
6
YG1
5
YG1
4
YG1
3
YG1
2
YG1
1
YG1
0
Reg
28
Bit
7-0
Name
YG1
7-0
Description
Y gain, 8 lsbs.
Bottom 8 bits of the luma gain
lsb = 1/256
DPC
000
001
010
011
100
101
110
111
Function
Reserved
TMC22051A
TMC22052A
TMC22053A
Reserved
TMC22151A
TMC22152A
TMC22153A
相關PDF資料
PDF描述
TMC22152A 8-Bit/10-Bit Digital Video Decoder(8位/10位數字視頻譯碼器)
TMC22153A 8-Bit/10-Bit Digital Video Decoder(8位/10位數字視頻譯碼器)
TMC22151 8-Bit/10-Bit Digital Video Decoder(8位/10位數字視頻譯碼器)
TMC22051 8-Bit Digital Video Decoder(8位數字視頻譯碼器)
TMC22052 8-Bit Digital Video Decoder(8位數字視頻譯碼器)
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