參數(shù)資料
型號: TMC2005
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 網(wǎng)絡(luò)接口
英文描述: 5 Port HUB Controller Device
中文描述: DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PQFP60
封裝: QFP-60
文件頁數(shù): 22/32頁
文件大小: 153K
代理商: TMC2005
SMSC DS – TMC2005
Page 22
Rev. 10/24/2000
CONNECTING THE TMC2005 WITH INTERNAL PLL
When using the TMC2005 at data rate 2.5Mbps or lower, it is not necessary to use internal PLL. Leave the loop
filter pins (RO, LP) open and connect AGS to the Ground. The pins for the analog power supply (AVSS, AVDD) may
connect to digital power supply. When using the TMC2005 at data rate 5Mbps or higher, the internal PLL has to be
used as a clock multiplier. PCB layout must follow the guidelines at Figure 10, refer to Notes 1 through 5.
FIGURE 10 - PLL PATTERN LAYOUT
Note 1: Prohibit the patterns for LP and RO from occupying the area of digital power supply. Use the area of
analog power supply between VAA and AVSS.
Note 2: Encircle the pattern between LP, RO and AGS with wide pattern of analog ground.
Note 3: Connect the analog power supply “VAA” with 0.1 uF condenser (a) with in 1/8 inch (~ 3.2mm) from VAA pin.
Note 4: In order to filter the jitter of low frequency, connect a 10 uF condenser (b) in parallel with the condenser (a).
Note 5: Place 0.1 uF bypass condenser (c) within inch (~ 6.4mm) from VDD3 and VSS3. Connect the ground
side of a condenser (c) at the place (*) where AVSS returns to GND plane.
PWR Plane
2400pF
0.1uF (c)
10uF (b)
0.1uF (a)
TMC2005
30
29
28
27
26
25
24
23
22
VSS5
VSS3
AVSS
AGS
LP
RO
VAA
VDD3
VDD4
68K
Gnd Plane
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