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參數(shù)資料
| 型號(hào)： | TM124MBK36B-60 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | DYNAMIC RAM MODULE |
| 中文描述： | 動(dòng)態(tài)隨機(jī)存儲(chǔ)器模塊 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 156K |
| 代理商： | TM124MBK36B-60 |
TM124MBK36B, TM124MBK36R 1048576 BY 36-BIT
TM248NBK36B, TM248NBK36R 2097152 BY 36-BIT
DYNAMIC RAMMODULE
SMMS137E – JANUARY 1991 – REVISEDJUNE 1995
2
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
TM248NBK36B (continued)
The TM124NBK36B is available in the double-sided BK leadless module for use with sockets.
The TM124NBK36B features RAS access times of 60 ns, 70 ns, and 80 ns. This device is rated for operation
from 0
°
C to 70
°
C
operation
TM124MBK36B
The TM124MBK36B operates as eight TMS44400DJs and one TMS44460DJ connected as shown in the
functional block diagram and Table 1. The parity bits are provided by the TMS44460DJ and are controlled by
RAS2. To ensure proper parity bit operation all memory accesses should include a RAS2 pulse. Refer to the
TMS44400 and TMS44460 data sheets for details of operation. The common I/O feature dictates the use of
early write cycles to prevent contention on D and Q.
TM248NBK36B
The TM248NBK36B operates as sixteen TMS44400DJs and two TMS44460DJs connected as shown in the
functional block diagram and Table 1. The parity bits are provided by the TMS44460DJ and are controlled by
RAS2 on side 1 and RAS3 on side 2. To ensure proper parity bit operation, all memory accesses should include
a RAS2 or RAS3 pulse. Refer to the TMS44400 and TMS44460 data sheets for details of operation. The
common I/O feature dictates the use of early write cycles to prevent contention on D and Q.
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| TM124MBK36B-70 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DYNAMIC RAM MODULE |
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| TM124MBK36C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DYNAMIC RAM MODULE |
| TM124MBK36F | 制造商:TI 制造商全稱:Texas Instruments 功能描述:36-BIT DRAM MODULE |
| TM124MBK36R | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DYNAMIC RAM MODULE |
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