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參數資料
| 型號： | TLV5639C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN |
| 中文描述： | 2.7 V至5.5 V低功耗12位數字到模擬，具有內部參考和斷電變換器 |
| 文件頁數： | 6/17頁 |
| 文件大小： | 242K |
| 代理商： | TLV5639C |
TLV5639C, TLV5639I
2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN
SLAS189 – MARCH 1999
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range, V
ref
= 2.048 V,
and V
ref
= 1.024 V, (unless otherwise noted)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t(FS)
ts(FS)
Output settling time full scale
Output settling time, full scale
RL = 10 k
See Note 11
CL = 100 pF,
Fast
1
3
μ
s
,
Slow
3.5
7
t(CC)
ts(CC)
Output settling time code to code
Output settling time, code to code
RL = 10 k
See Note 12
CL = 100 pF,
Fast
0.5
1.5
μ
s
,
Slow
1
2
SR
Slew rate
RL = 10 k
See Note 13
CL = 100 pF,
Fast
6
10
V/
μ
s
,
Slow
1.2
1.7
Glitch energy
DIN = 0 to 1,
CS = VDD
fCLK = 100 kHz,
5
nV–S
SNR
Signal-to-noise ratio
73
78
SINAD
Signal-to-noise + distortion
fs = 480 kSPS, fout = 1 kHz,
fB = 20 kHz,
CL = 100 pF
CL = 100 F
RL = 10 k
,
61
67
dB
THD
Total harmonic distortion
–69
–62
SFDR
NOTES: 11. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFDF or 0xFDF to 0x020.
12. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of one count.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
Spurious free dynamic range
63
74
digital input timing requirements
MIN
NOM
MAX
UNIT
tsu(CS–WE)
tsu(D)
tsu(R)
th(DR)
tsu(WE-LD)
twH(WE)
tw(LD)
Setup time, CS low before negative WE edge
15
ns
Setup time, data ready before positive WE edge
10
ns
Setup time, REG ready before positive WE edge
20
ns
Hold time, data and REG held valid after positive WE edge
5
ns
Setup time, positive WE edge before LDAC low
5
ns
Pulse duration, WE high
20
ns
Pulse duration, LDAC low
23
ns
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