參數(shù)資料
型號: TLV5639C
廠商: Texas Instruments, Inc.
英文描述: 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN
中文描述: 2.7 V至5.5 V低功耗12位數(shù)字到模擬,具有內(nèi)部參考和斷電變換器
文件頁數(shù): 11/17頁
文件大?。?/td> 242K
代理商: TLV5639C
TLV5639C, TLV5639I
2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN
SLAS189 – MARCH 1999
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
general function
The TLV5639 is a 12-bit, single supply DAC, based on a resistor string architecture. It consists of a parallel
interface, a speed and power down control logic, a programmable internal reference, a resistor string, and a
rail-to-rail output buffer. The output voltage (full scale determined by reference) is given by:
2 REF0x1000[V]
Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power
on reset initially puts the internal latches to a defined state (all bits zero).
parallel interface
The device latches data on the positive edge of WE. It must be enabled with CS low. Whether the data is written
to the DAC holding latch or the control register depends on REG. REG = 0 selects the DAC holding latch,
REG = 1 selects the control register. LDAC low updates the DAC with the value in the holding latch. LDAC is
an asynchronous input and can be held low, if a separate update is not necessary. However, to control the DAC
using the load feature, there should be approximately a 5 ns delay after the positive WE edge before driving
LDAC low.
Address
Decoder
A(0–15)
IS
WE
D(0–15)
CS
LDAC
WE
D(0–11)
TMS320C2XX, 5X
TLV5639
Address
Decoder
A(0–15)
TCLK0
R/W
D(0–15)
CS
LDAC
WE
D(0–11)
TMS320C3X
TLV5639
IOSTROBE
REG
> = 1
REG
Figure 11
data format
The TLV5639 writes data either to the DAC holding latch or to the control register, depending on the level of the
REG input.
Data destination:
REG = 0
DAC holding latch
REG = 1
control register
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