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參數(shù)資料
| 型號： | TLV5638JG |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | MOSFET P-CH 20V 5.3A 8-SOIC |
| 中文描述： | 2.7 V至5.5 V低功耗雙通道12位數(shù)字至模擬轉(zhuǎn)換器，具有內(nèi)部參考和斷電 |
| 文件頁數(shù)： | 4/19頁 |
| 文件大小： | 289K |
| 代理商： | TLV5638JG |
TLV5638
2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS225A – JUNE 1999 – REVISED JANUARY 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions, V
ref
= 2.048 V, V
ref
= 1.024 V
(unless otherwise noted)
power supply
PARAMETER
TEST CONDITIONS
TLV5638C,
TLV5638I
MIN
TYP
TLV5638Q,
TLV5638M
MIN
TYP
UNIT
MAX
MAX
VDD = 5 V,
Int. ref.
Fast
4.3
5.2
4.3
5.4
mA
Slow
2.2
2.7
2.2
2.7
No load,
All inputs = AGND
or VDD,
DAC latch = 0x800
VDD = 3 V,
Int. ref.
Fast
3.8
4.7
3.8
4.9
mA
IDD
Power supply current
Slow
1.8
2.3
1.8
2.3
VDD = 5 V,
Ext. ref.
Fast
3.9
4.8
3.9
5.0
mA
Slow
1.8
2.2
1.8
2.2
VDD = 3 V,
Ext. ref.
Fast
3.5
4.3
3.5
4.5
mA
Slow
1.5
1.9
1.5
1.9
Power-down supply current
0.01
10
0.01
10
μ
A
PSRR
Power supply rejection ratio
Zero scale, See Note 2
–65
–65
dB
Full scale, See Note 3
–65
–65
NOTES:
2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:
PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]
3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]
static DAC specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
12
bits
INL
Integral nonlinearity end point adjusted
Integral nonlinearity, end point adjusted
See Note 4
C and I suffixes
±
1.7
±
1.7
±
0.4
±
4
±
6
±
1
LSB
Q and M suffixes
LSB
DNL
Differential nonlinearity
See Note 5
LSB
EZS
EZS TC
Zero-scale error (offset error at zero scale)
See Note 6
±
24
mV
Zero-scale-error temperature coefficient
See Note 7
10
ppm/
°
C
% full
scale V
ppm/
°
C
EG
Gain error
See Note 8
±
0.6
EG TC
NOTES:
Gain error temperature coefficient
4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 32 to 4095.
5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
7. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(Tmax) – EZS(Tmin)]/Vref
×
106/(Tmax – Tmin).
8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 k
excluding the effects of the zero-error.
9. Gain temperature coefficient is given by: EGTC = [EG(Tmax) – EG (Tmin)]/Vref
×
106/(Tmax – Tmin).
See Note 9
10
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