參數(shù)資料
型號: TLV5638JG
廠商: Texas Instruments, Inc.
英文描述: MOSFET P-CH 20V 5.3A 8-SOIC
中文描述: 2.7 V至5.5 V低功耗雙通道12位數(shù)字至模擬轉(zhuǎn)換器,具有內(nèi)部參考和斷電
文件頁數(shù): 11/19頁
文件大?。?/td> 289K
代理商: TLV5638JG
TLV5638
2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS225A – JUNE 1999 – REVISED JANUARY 2000
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
serial interface
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling
edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the
target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 13 shows examples of how to connect the TLV5638 to TMS320, SPI
, and Microwire
.
TMS320
DSPFSX
CLKX
DX
TLV5638
CS
SCLK
DIN
SPI
I/O
SCK
MOSI
TLV5638
CS
SCLK
DIN
Microwire
I/O
SO
SK
TLV5638
CS
SCLK
DIN
Figure 13. Three-Wire Interface
Notes on SPI
and Microwire
: Before the controller starts the data transfer, the software has to generate a
falling edge on the pin connected to FS. If the word width is 8 bits (SPI
and Microwire
), two write operations
must be performed to program the TLV5638. After the write operation(s), the holding registers or the control
register are updated automatically on the 16
th
positive clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
sclkmax
1
t
whmin
t
wlmin
20 MHz
The maximum update rate is:
f
updatemax
1
16 t
whmin
t
wlmin
1.25 MHz
Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5638 has to be considered, too.
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TLV5638D 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
TLV5638FK 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
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