參數(shù)資料
型號(hào)： TLV5637D
廠商： Texas Instruments, Inc.
英文描述： 2.7 V TO 5.5 V LOW POWER DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
中文描述： 2.7 V至5.5 V低功耗雙10位數(shù)字至模擬轉(zhuǎn)換器，具有內(nèi)部參考和斷電
文件頁(yè)數(shù)： 5/17頁(yè)
文件大小： 240K
代理商： TLV5637D
TLV5637
2.7 V TO 5.5 V LOW POWER DUAL 10-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS224 –JUNE 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)
reference pin configured as output (REF)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vref(OUTL)
Vref(OUTH)
Iref(source)
Iref(sink)
Low reference voltage
1.003
1.024
1.045
V
High reference voltage
VDD > 4.75 V
2.027
2.048
2.069
V
Output source current
1
mA
Output sink current
–1
mA
Load capacitance
100
pF
PSRR
Power supply rejection ratio
–65
dB
reference pin configured as input (REF)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
RI
CI
Input voltage
0
VDD–1.5
V
Input resistance
10
M
pF
MHz
Input capacitance
5
Reference input bandwidth
REF = 0 2 V
REF = 0.2 Vpp + 1.024 V dc
+ 1 024 V dc
Fast
1.3
Slow
525
kHz
Reference feedthrough
REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)
–80
dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
μ
A
μ
A
pF
IIH
IIL
Ci
High-level digital input current
VI = VDD
VI = 0 V
1
Low-level digital input current
–1
Input capacitance
8
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
0.8
MAX
2.4
UNIT
t(FS)
ts(FS)
Output settling time full scale
Output settling time, full scale
RL = 10 k
See Note 11
CL = 100 pF,
Fast
μ
s
,
Slow
2.8
5.5
t(CC)
ts(CC)
Output settling time code to code
Output settling time, code to code
RL = 10 k
See Note 12
CL = 100 pF,
Fast
0.4
1.2
μ
s
,
Slow
0.8
1.6
SR
Slew rate
RL = 10 k
See Note 13
CL = 100 pF,
Fast
12
V/
μ
s
,
Slow
1.8
Glitch energy
DIN = 0 to 1,
CS = VDD
fCLK = 100 kHz,
5
nV–S
SNR
Signal-to-noise ratio
53
56
S/(N+D)
Signal-to-noise + distortion
fs = 480 kSPS, fout
RL = 10 k
,
50
54
dB
THD
Total harmonic distortion
CL = 100 pF
,
–61
–50
SFDR
NOTES: 11. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFDF or 0xFDF to 0x020 respectively. Not tested, assured by design.
12. Settling time is the time for the output signal to remain within
±
0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
Spurious free dynamic range
51
62
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