參數(shù)資料
型號： TLV5637D
廠商： Texas Instruments, Inc.
英文描述： 2.7 V TO 5.5 V LOW POWER DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
中文描述： 2.7 V至5.5 V低功耗雙10位數(shù)字至模擬轉(zhuǎn)換器，具有內(nèi)部參考和斷電
文件頁數(shù)： 11/17頁
文件大小： 240K
代理商： TLV5637D
TLV5637
2.7 V TO 5.5 V LOW POWER DUAL 10-BIT DIGITAL-TO-ANALOG
CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS224 –JUNE 1999
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
serial clock frequency and update rate
The maximum serial clock frequency is given by:
f
sclkmax
1
t
whmin
t
wlmin
20 MHz
The maximum update rate is:
f
updatemax
1
16 t
whmin
t
wlmin
1.25 MHz
Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5637 has to be considered, too.
data format
The 16-bit data word for the TLV5637 consists of two parts:
Program bits (D15..D12)
New data (D11..D0)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
R1
SPD
PWR
R0
12 Data bits
SPD: Speed control bit
PWR: Power control bit
1
→
fast mode
1
→
power down
0
→
slow mode
0
→
normal operation
The following table lists the possible combination of the register select bits:
register select bits
R1
R0
REGISTER
0
0
Write data to DAC B and BUFFER
0
1
Write data to BUFFER
1
0
Write data to DAC A and update DAC B with BUFFER content
1
1
Write data to control register
The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected,
then the 12 data bits determine the new DAC value:
data bits: DAC A, DAC B and BUFFER
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
New DAC Value
0
0
If control is selected, then D1, D0 of the 12 data bits are used to program the reference voltage:
data bits: CONTROL
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
REF1
REF0
X: don’t care
REF1 and REF0 determine the reference source and, if internal reference is selected, the reference voltage.
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