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參數(shù)資料
| 型號： | TLV5621IDRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 75 us SETTLING TIME, 8-BIT DAC, PDSO14 |
| 封裝： | GREEN, PLASTIC, SOIC-14 |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 321K |
| 代理商： | TLV5621IDRG4 |
SLAS138B
–
APRIL
1996
–
REVISED
FEBRUAR
Y
1997
TL
V5621I
LOW
-POWER
QUADRUPLE
8-BIT
DIGIT
AL-T
O-ANALOG
CONVERTER
T
emp
late
R
e
lease
D
ate:
7
–
11
–
94
4
POST
OFFICE
BOX
655303
DALLAS,
TEXAS
75265
CLK
RS
MODE
RNG
A
RNG
B
RNG
C
RNG
D
SIA
SIB
SIC
SID
ACT
DATA
DAC
EN
(Tied High)
NOTE A: Twelve zeros enable word synchronization and the output can change after the leading edge of CLK depending on the data in the latches.
Figure 1. Register Write Operation Following Noise or Undefined Levels on DATA or CLK (Single-Buffer Mode)
CLK
RS
MODE
RNG
A
RNG
B
RNG
C
RNG
D
SIA
SIB
SIC
SID
ACT
DATA
DAC
EN
(Tied High)
NOTE A: EN is held high and data is written to a DAC register. The data is latched to the output of the DAC on the falling edge of the last CLK of the control word, where the
mode is set.
RS
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 2. First Nonzero Write Operation After Startup (EN = High)
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