參數(shù)資料
型號(hào)： TLV320DAC32IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, DAC WITH PROGRAMMABLE PLL, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁(yè)數(shù)： 38/69頁(yè)
文件大?。?/td> 1242K
代理商： TLV320DAC32IRHBT
www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008
Page 0 / Register 13:
Headset / Button Press Detection Register A (continued)
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D1-D0
R/W
00
Headset Glitch Suppression Debounce Control for Button Press
00: Debounce = 0msec
01: Debounce = 8msec(sampled with 1ms clock)
10: Debounce = 16msec(sampled with 2ms clock)
11: Debounce = 32msec(sampled with 4ms clock)
Page 0 / Register 14:
Headset / Button Press Detection Register B
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7
R/W
0
Driver Capacitive Coupling
0: Programs high-power outputs for capless driver configuration
1: Programs high-power outputs for ac-coupled driver configuration
D6(1)
R/W
0
High Power Stereo Output Driver Configuration A
Note: do not set bits D6 and D3 both high at the same time.
0: A stereo fully-differential output configuration is not being used
1: A stereo fully-differential output configuration is being used
D5
R
0
Button Press Detection Flag
This register is a sticky bit, and will stay set to 1 after a button press has been detected, until the
register is read. Upon reading this register, the bit is reset to zero.
0: A button press has not been detected
1: A button press has been detected
D4
R
0
Headset Detection Flag
0: A headset has not been detected
1: A headset has been detected
D3(1)
R/W
0
Stereo Output Driver Configuration B
Note: do not set bits D6 and D3 both high at the same time.
0: A stereo pseudo-differential output configuration is not being used
1: A stereo pseudo-differential output configuration is being used
D2–D0
R
000
Reserved. Write only zeros to these bits.
(1)
Do not set D6 and D3 to 1 simultaneously
Page 0 / Register 15–24:
Reserved Registers
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7-D0
R/W
00000000
Reserved. Only write zeroes to these bits.
Page 0 / Register 25:
MICBIAS Control Register
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
MICBIAS Level Control
00: MICBIAS output is powered down
01: MICBIAS output is powered to 2.0 V
10: MICBIAS output is powered to 2.5 V
11: MICBIAS output is connected to AVDD_DAC
D5–D3
R
000
Reserved. Write only zeros to these register bits.
D2–D0
R
XXX
Read only bits. Do not write to these register bits.
Page 0 / Register 26–36:
Reserved Registers
BIT
READ/
RESET
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
00000000
Reserved. Only write zeroes to these bits.
Copyright 2006–2008, Texas Instruments Incorporated
43
Product Folder Link(s): TLV320DAC32
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