參數(shù)資料
型號： TLV320AIC3120IRHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： 音頻／視頻放大
英文描述： AUDIO AMPLIFIER, PQCC32
封裝： 5 X 5 MM, GREEN, PLASTIC, QFN-32
文件頁數(shù)： 124/150頁
文件大小： 1507K
代理商： TLV320AIC3120IRHBT
LD(n)
LD (n+1)
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
0
3
2
1
-
1
-
2
N N N
-
3
RD(n)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD(n)
LD(n+1)
BIT
CLOCK
DATA
-
1
-
2
-
3
2
1
0
3
-
1
-
2
-
3
0
3
2
1
-
1
-
2
N N N
-
3
RD(n)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
LD(n)=n'thsampleofleftchanneldata
RD(n)=n'thsampleofrightchanneldata
LD(n)
LD (n+1)
BIT
CLOCK
DATA
N
-
1
N
-
2
N
-
3
2
1
0
3
N
-
1
N
-
2
N
-
3
0
3
2
1
N
-
1
N
-
2
N
-
3
RD(n)
WORD
CLOCK
LEFT CHANNEL
RIGHT CHANNEL
www.ti.com
SLAS653 – FEBRUARY 2010
5.8.1.4
DSP Mode
The audio interface of the TLV320AIC3120 can be put into DSP mode by programming page 0 / register
27, bits D7–D6 = 01. In DSP mode, the falling edge of the word clock starts the data transfer with the
left-channel data first and immediately followed by the right-channel data. Each data bit is valid on the
falling edge of the bit clock.
Figure 5-44. Timing Diagram for DSP Mode
Figure 5-45. Timing Diagram for DSP Mode With Offset = 1
Figure 5-46. Timing Diagram for DSP Mode With Offset = 0 and Bit Clock Inverted
For DSP mode, the number of bit clocks per frame should be greater than or equal to twice the
programmed word length of the data. Also, the programmed offset value should be less than the number
of bit clocks per frame by at least the programmed word length of the data.
5.8.2
Primary and Secondary Digital Audio Interface Selection
The audio serial interface on the TLV320AIC3120 has extensive I/O control to allow communication with
two independent processors for audio data. Only one processor can communicate with the device one at
Copyright 2010, Texas Instruments Incorporated
APPLICATION INFORMATION
75
Product Folder Link(s): TLV320AIC3120
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